公开(公告)号：US20130010560A1

公开(公告)日：2013-01-10

申请号：US13535075

申请日：2012-06-27

Applicant: Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

Inventor： Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

IPC: H03F3/45 ,  G11C7/06

CPC classification number: G11C7/067 ,  G11C7/065

Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.

Abstract translation: 电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。 第一电流镜电路具有参考端和镜像端。 第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。 第二个当前次级电路具有参考端和镜像端。 第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

公开(公告)号：US20130003445A1

公开(公告)日：2013-01-03

申请号：US13609930

申请日：2012-09-11

Applicant: Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C11/40 ,  H01L21/8244

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line

Abstract translation: 静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。 第一晶体管耦合在第一节点和第一位线之间。 第二晶体管耦合在第二节点和第二位线之间。 第三晶体管与第一节点耦合。 第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。 第五晶体管耦合在第三晶体管和第三位线之间

公开(公告)号：US08279684B2

公开(公告)日：2012-10-02

申请号：US12842189

申请日：2010-07-23

Applicant: Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

Inventor： Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC: G11C7/00

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

Abstract translation: 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

公开(公告)号：US20120195139A1

公开(公告)日：2012-08-02

申请号：US13443619

申请日：2012-04-10

Applicant: Hsu-Shun CHEN ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Chung-Yi WU ,  Chih-Chieh CHIU

Inventor： Hsu-Shun CHEN ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Chung-Yi WU ,  Chih-Chieh CHIU

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C7/1048 ,  G11C5/14

Abstract: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

Abstract translation: 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

公开(公告)号：US20120182792A1

公开(公告)日：2012-07-19

申请号：US13008992

申请日：2011-01-19

Applicant: Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Hsu-Shun CHEN ,  Chung-Ji LU ,  Cheng-Hung LEE ,  Hung-Jen LIAO

Inventor： Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Hsu-Shun CHEN ,  Chung-Ji LU ,  Cheng-Hung LEE ,  Hung-Jen LIAO

IPC: G11C11/413 ,  G11C5/14

CPC classification number: G11C11/413

Abstract: A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.

Abstract translation: SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

公开(公告)号：US20120153433A1

公开(公告)日：2012-06-21

申请号：US12974896

申请日：2010-12-21

Applicant: Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

Inventor： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

IPC: H01L23/552 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/0248 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17517 ,  H01L2224/81455 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.

Abstract translation: 一种器件包括：裸片，包括主电路和耦合到主电路的第一焊盘。 包括第二垫的工件被结合到模具。 第一多个微凸块在第一和第二焊盘之间串联电耦合。 多个微型凸块中的每一个包括连接模具的第一端和连接工件的第二端。 微凸块与模具和工件结合。 第二焊盘电耦合到微凸起。

公开(公告)号：US07952911B2

公开(公告)日：2011-05-31

申请号：US12111905

申请日：2008-04-29

Applicant: Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

Inventor： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

IPC: G11C11/00

CPC classification number: G11C5/063 ,  G11C11/419

Abstract: This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.

Abstract translation: 本发明公开了一种静态随机存取存储器（SRAM）单元阵列结构，其包括耦合到一列SRAM单元的第一和第二位线，第一和第二位线基本上彼此平行并由第一金属 层，并且第一导线被放置在第一和第二位线之间并跨越SRAM单元的列而不与其形成导电耦合，第一导电线也由第一金属层形成。

公开(公告)号：US20110090753A1

公开(公告)日：2011-04-21

申请号：US12885826

申请日：2010-09-20

Applicant: Cheng Hung LEE ,  Chung-Yi WU ,  Hsu-Shun CHEN ,  Chung-Ji LU

Inventor： Cheng Hung LEE ,  Chung-Yi WU ,  Hsu-Shun CHEN ,  Chung-Ji LU

IPC: G11C5/14

CPC classification number: G11C11/413

Abstract: An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power.

Abstract translation: SRAM包括被配置用于使用不同的电压电平在不同的操作模式下工作的电路，其中基于操作模式调节电压电平和因此的电流泄漏。 例如，在正常工作模式下，SRAM将作为其他SRAM消耗电力。 在深度睡眠模式下，SRAM宏中的位单元的电源电压（例如，VDDI）降低SRAM电源电压（例如VDD）的约20-40％，足以将数据保留在位单元中。 当不需要访问SRAM时，SRAM在睡眠模式下运行，消耗很少或没有电源。

公开(公告)号：US20110063894A1

公开(公告)日：2011-03-17

申请号：US12877695

申请日：2010-09-08

Applicant: Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C11/00 ,  H01R43/00

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line

Abstract translation: 静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。 第一晶体管耦合在第一节点和第一位线之间。 第二晶体管耦合在第二节点和第二位线之间。 第三晶体管与第一节点耦合。 第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。 第五晶体管耦合在第三晶体管和第三位线之间

公开(公告)号：US20100315859A1

公开(公告)日：2010-12-16

申请号：US12750430

申请日：2010-03-30

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: G11C11/00 ,  G11C8/16

CPC classification number: G11C8/16 ,  G11C11/412

Abstract: An integrated circuit structure includes a first static random access memory (SRAM) cell including a first read-port and a first write-port; and a second SRAM cell including a second read-port and a second write-port. The first SRAM cell and the second SRAM cell are in a same row and arranged along a row direction. A first word-line is coupled to the first SRAM cell. A second word-line is coupled to the second SRAM cell. A read bit-line is coupled to the first SRAM cell and the second SRAM cell, wherein the read bit-line extends in a column direction perpendicular to the row direction. A write bit-line is coupled to the first SRAM cell and the second SRAM cell.

Abstract translation: 集成电路结构包括包括第一读取端口和第一写入端口的第一静态随机存取存储器（SRAM）单元; 以及包括第二读取端口和第二写入端口的第二SRAM单元。 第一SRAM单元和第二SRAM单元位于同一行中并沿着行方向布置。 第一字线耦合到第一SRAM单元。 第二字线耦合到第二SRAM单元。 读位线耦合到第一SRAM单元和第二SRAM单元，其中读位线在垂直于行方向的列方向上延伸。 写位线耦合到第一SRAM单元和第二SRAM单元。