公开(公告)号：US08334174B2

公开(公告)日：2012-12-18

申请号：US12862473

申请日：2010-08-24

Applicant: Chiang-Cheng Chang ,  Hsin-Yi Liao ,  Hsu-Hsi Chang ,  Shih-Kuang Chiu

Inventor： Chiang-Cheng Chang ,  Hsin-Yi Liao ,  Hsu-Hsi Chang ,  Shih-Kuang Chiu

IPC: H01L21/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result.

Abstract translation: 芯片级封装的制造方法包括：在载板上设置芯片并将芯片嵌入具有硬层和软层的复合板中; 并移除载体板以进行再分布层（RDL）处理，从而解决了将由芯片直接附着在粘合膜上的常规问题，例如由热引起的薄膜软化，密封剂溢出，芯片偏移和污染， 所有这些都可能导致在随后的RDL过程中布线层和芯片电极垫之间的电连接不良，甚至结果导致废物。

公开(公告)号：US20120086117A1

公开(公告)日：2012-04-12

申请号：US12965215

申请日：2010-12-10

Applicant: Chiang-Cheng Chang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu

Inventor： Chiang-Cheng Chang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu

IPC: H01L23/36 ,  H01L21/60

CPC classification number: H01L23/5389 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511

Abstract: A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Abstract translation: 嵌入芯片的封装以及制造嵌入式芯片封装的方法。 嵌入式芯片的封装包括具有与第一表面相对的第一表面和第二表面的电介质层; 形成在电介质层中并从电介质层的第二表面露出的多个导电柱; 嵌入在介电层中的芯片; 形成在电介质层的第一表面上的电路层; 形成在所述电介质层中的多个导电盲孔，允许所述电路层经由所述导电盲孔通向芯片和每个导电柱电连接; 以及形成在电介质层和电路层的第一表面上的第一焊料掩模层，从而根据需要使用导电柱来与其他电子器件外部连接以形成堆叠结构。 因此，可以有效地简化制造过程。

公开(公告)号：US08680692B2

公开(公告)日：2014-03-25

申请号：US13440180

申请日：2012-04-05

Applicant: Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L23/28

CPC classification number: H01L21/56 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/673 ,  H01L21/67333 ,  H01L21/67763 ,  H01L21/68 ,  H01L21/683 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract translation: 半导体封装的制造方法包括以下步骤：提供在其表面上形成有凹部和脱模层的载体; 在凹部中的脱模层上设置芯片; 在芯片和释放层上形成密封剂; 去除释放层和载体; 并在密封剂和芯片上形成电路结构。 凹部的设计有助于芯片对准以防止其移位，从而提高产品的可靠性。 还提供了通过制造方法制造的半导体封装。

公开(公告)号：US20130187285A1

公开(公告)日：2013-07-25

申请号：US13440180

申请日：2012-04-05

Applicant: Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L21/50 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/673 ,  H01L21/67333 ,  H01L21/67763 ,  H01L21/68 ,  H01L21/683 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract translation: 半导体封装的制造方法包括以下步骤：提供在其表面上形成有凹部和释放层的载体; 在凹部中的脱模层上设置芯片; 在芯片和释放层上形成密封剂; 去除释放层和载体; 并在密封剂和芯片上形成电路结构。 凹部的设计有助于芯片对准以防止其移位，从而提高产品的可靠性。 还提供了通过制造方法制造的半导体封装。

公开(公告)号：US20120013006A1

公开(公告)日：2012-01-19

申请号：US12955613

申请日：2010-11-29

Applicant: Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

Inventor： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/485 ,  H01L21/786

CPC classification number: H01L21/561 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/96 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

Abstract: A fabrication method of a chip scale package is provided, which includes forming a protection layer on the active surface of a chip and fixing the inactive surface of the chip to a transparent carrier; performing a molding process; removing the protection layer from the chip and performing a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the wiring layer formed in the RDL process and the chip electrode pads and even waste product as a result. Further, the transparent carrier employed in the invention can be separated by laser and repetitively used in the process to help reduce the fabrication cost.

Abstract translation: 提供了一种芯片级封装的制造方法，其包括在芯片的有源表面上形成保护层并将芯片的非活性表面固定到透明载体上; 进行成型工序; 从芯片上除去保护层并执行再分配层（RDL）工艺，从而解决了将芯片直接附着在粘合膜上所引起的常规问题，例如由热引起的膜软化，密封剂溢出，翘曲，芯片偏差和 污染导致在RDL工艺中形成的布线层与芯片电极焊盘之间的电连接不良，甚至结果导致废品。 此外，本发明中使用的透明载体可以通过激光分离并在该过程中重复使用以帮助降低制造成本。

公开(公告)号：US20130228915A1

公开(公告)日：2013-09-05

申请号：US13534664

申请日：2012-06-27

Applicant: Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L21/78 ,  H01L23/488

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

Abstract translation: 半导体封装的制造方法包括以下步骤：在具有凹部的载体上形成剥离层; 在载体的凹部中将剥离层设置在剥离层上; 在芯片和释放层上形成密封剂; 在所述密封剂上形成结合层; 去除剥离层和载体以暴露芯片的活性表面; 以及在密封剂和芯片上形成电路结构。 由于释放层仅与芯片和密封剂稍微粘合，所以本发明避免了在不兼容的CTE引起的热循环期间整个结构的翘曲。

公开(公告)号：US20120018870A1

公开(公告)日：2012-01-26

申请号：US12862473

申请日：2010-08-24

Applicant: Chiang-Cheng Chang ,  Hsin-Yi Liao ,  Hsu-His Chang ,  Shih-Kuang Chiu

Inventor： Chiang-Cheng Chang ,  Hsin-Yi Liao ,  Hsu-His Chang ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result.

Abstract translation: 芯片级封装的制造方法包括：在载板上设置芯片并将芯片嵌入具有硬层和软层的复合板中; 并移除载体板以进行再分布层（RDL）处理，从而解决了将由芯片直接附着在粘合膜上的常规问题，例如由热引起的薄膜软化，密封剂溢出，芯片偏移和污染， 所有这些都可能导致在随后的RDL过程中布线层和芯片电极垫之间的电连接不良，甚至结果导致废物。