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    HV interconnection solution using floating conductors
    11.
    发明授权
    HV interconnection solution using floating conductors 有权
    使用浮动导体的HV互连解决方案

    公开(公告)号：US08629513B2

    公开(公告)日：2014-01-14

    申请号：US13007220

    申请日：2011-01-14

    Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC: H01L29/78

    CPC classification number: H01L29/7835 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/861

    Abstract: A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.

    Abstract translation: 一种器件包括半导体衬底中的第一和第二重掺杂区域。 绝缘区域在半导体衬底中具有至少一部分，其中绝缘区域与第一和第二重掺杂区域相邻。 栅极电介质形成在半导体衬底之上并且具有在绝缘区域的一部分上的部分。 栅极形成在栅极电介质上。 浮动导体在绝缘区域上方和上方重叠。 金属线包括在浮动导体上方并垂直重叠的部分，其中金属线与第二重掺杂区耦合并承载第二重掺杂区的电压。

    HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME
    13.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME 有权
    高电子移动性晶体管及其形成方法

    公开(公告)号：US20130168685A1

    公开(公告)日：2013-07-04

    申请号：US13338962

    申请日：2011-12-28

    Applicant: Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chen-Ju YU ,  Fu-Chih YANG ,  Chun Lin TSAI

    Inventor： Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chen-Ju YU ,  Fu-Chih YANG ,  Chun Lin TSAI

    IPC: H01L29/778 ,  H01L21/338 ,  H01L29/205

    CPC classification number: H01L29/66462 ,  H01L21/02271 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/432 ,  H01L29/7786 ,  H01L2924/0002

    Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. The gate electrode includes a refractory metal. A depletion region is disposed in the carrier channel and under the gate electrode.

    Abstract translation: 高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 源特征和漏极特征设置在第二III-V复合层上。 p型层设置在源特征和漏极特征之间的第二III-V化合物层的一部分上。 栅电极设置在p型层上。 栅电极包括难熔金属。 耗尽区域设置在载流子通道中和栅电极下方。

    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    15.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权
    半导体结构及其形成方法

    公开(公告)号：US20130015460A1

    公开(公告)日：2013-01-17

    申请号：US13180268

    申请日：2011-07-11

    Applicant: Po-Chih CHEN ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chun-Wei HSU ,  Fu-Chih YANG ,  Chun Lin TSAI

    Inventor： Po-Chih CHEN ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chun-Wei HSU ,  Fu-Chih YANG ,  Chun Lin TSAI

    IPC: H01L29/778 ,  H01L21/335 ,  H01L29/205

    CPC classification number: H01L27/11578 ,  H01L21/28575 ,  H01L27/11565 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7787

    Abstract: An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.

    Abstract translation: 本公开的实施例包括半导体结构。 半导体结构包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 在第一III-V化合物层和第二III-V化合物层之间界定界面。 栅极设置在第二III-V复合层上。 源极特征和漏极特征设置在栅极的相对侧上。 源特征和漏极特征中的每一个包括至少部分地嵌入第二III-V化合物层中的对应金属特征。 相应的金属间化合物是每个金属特征的基础。 每个金属间化合物接触位于界面处的载体通道。

    High Voltage Resistor With Pin Diode Isolation
    16.
    发明申请
    High Voltage Resistor With Pin Diode Isolation 有权
    高压电阻与引脚二极管隔离

    公开(公告)号：US20120319240A1

    公开(公告)日：2012-12-20

    申请号：US13160030

    申请日：2011-06-14

    Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC: H01L29/8605 ,  H01L21/20

    CPC classification number: H01L29/0649 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/761 ,  H01L21/76202 ,  H01L23/528 ,  H01L27/0676 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/6609 ,  H01L29/8605 ,  H01L29/868

    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

    Abstract translation: 提供一种高压半导体器件，其包括形成在衬底中的PIN二极管结构。 PIN二极管包括位于第一掺杂阱和第二掺杂阱之间的本征区。 第一和第二掺杂阱具有与内部区域相反的掺杂极性和更大的掺杂浓度水平。 半导体器件包括形成在第一掺杂阱的一部分上的绝缘结构。 半导体器件包括形成在绝缘结构上的细长电阻器件。 电阻器件分别设置在电阻器件的相对端处的第一和第二部分。 半导体器件包括形成在电阻器件上的互连结构。 互连结构包括：电耦合到第一掺杂阱的第一接触和电耦合到位于第一和第二部分之间的电阻器的第三部分的第二接触。

    HIGH VOLTAGE DEVICE WITH A PARALLEL RESISTOR
    18.
    发明申请
    HIGH VOLTAGE DEVICE WITH A PARALLEL RESISTOR 有权
    具有并联电阻的高电压装置

    公开(公告)号：US20140021560A1

    公开(公告)日：2014-01-23

    申请号：US13551262

    申请日：2012-07-17

    Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

    Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

    IPC: H01L27/06 ,  H01L21/8234

    CPC classification number: H01L27/0629

    Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.

    Abstract translation: 提供高压半导体器件。 高电压半导体器件包括具有栅极，源极和漏极的晶体管。 源极和漏极形成在掺杂衬底中并且由衬底的漂移区域分离。 栅极形成在漂移区域上以及源极和漏极之间。 晶体管被配置为处理至少几百伏特的高电压条件。 高电压半导体器件包括在晶体管的源极和漏极之间形成的电介质结构。 电介质结构突出进出基板。 电介质结构的不同部分具有不均匀的厚度。 高电压半导体器件包括在电介质结构上形成的电阻器。 电阻器具有大致均匀间隔开的多个绕组段。

    Source tip optimization for high voltage transistor devices
    19.
    发明授权
    Source tip optimization for high voltage transistor devices 有权
    高压晶体管器件的源尖优化

    公开(公告)号：US08629026B2

    公开(公告)日：2014-01-14

    申请号：US12944959

    申请日：2010-11-12

    Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC: H01L21/22 ,  H01L21/331 ,  H01L21/336 ,  H01L21/38 ,  H01L21/425

    CPC classification number: H01L29/7816 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7835

    Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

    Abstract translation: 本公开提供了一种用于制造高压半导体器件的方法。 该方法包括在衬底中指定第一，第二和第三区域。 第一和第二区域分别是将形成半导体器件的源极和漏极的区域。 第三区域分隔第一和第二区域。 该方法还包括至少部分地在第三区域上形成开槽的注入掩模层。 该方法还包括将掺杂剂注入到第一，第二和第三区域中。 开槽植入物掩模层在植入期间保护其下方的第三区域的部分。 该方法还包括以使得掺杂剂在第三区域中扩散的方式退火衬底。

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