公开(公告)号：US20050067701A1

公开(公告)日：2005-03-31

申请号：US10605444

申请日：2003-09-30

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

CPC分类号： H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

摘要翻译： 一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的上表面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

公开(公告)号：US20070290272A1

公开(公告)日：2007-12-20

申请号：US11846595

申请日：2007-08-29

申请人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

发明人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

IPC分类号： H01L29/00

CPC分类号： H01L27/016

摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

摘要翻译： 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

公开(公告)号：US20070275534A1

公开(公告)日：2007-11-29

申请号：US11839106

申请日：2007-08-15

申请人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

发明人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

IPC分类号： H01L21/331

CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。

公开(公告)号：US20070190760A1

公开(公告)日：2007-08-16

申请号：US11275544

申请日：2006-01-13

申请人： Douglas Coolbaugh ,  Hanyi Ding ,  Ebenezer Eshun ,  Michael Gordon ,  Zhong-Xiang He ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Hanyi Ding ,  Ebenezer Eshun ,  Michael Gordon ,  Zhong-Xiang He ,  Anthony Stamper

IPC分类号： H01L21/425

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

摘要翻译： 形成在集成电路的后端的平行电容器采用与后端（具有相同材料，厚度等）的该级别上的其它互连件同时形成的导电电容器板。 使用与后端（优选双镶嵌）级别上的其它互连件相同的工艺将电容器板设置在层间电介质中。 一些版本的电容器在板中具有穿孔，并且垂直导电构件连接相同极性的所有板，从而与实心板相比增加了可靠性，节省了空间并增加了电容密度。

公开(公告)号：US20070152332A1

公开(公告)日：2007-07-05

申请号：US11306596

申请日：2006-01-04

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to integrated circuits that comprise via-level wirings and/or devices. Specifically, an integrate circuit of the present invention comprises a first line level and a second line level spaced apart from each other, with a via level therebetween. The first and second line levels both comprise metal wirings and/or electronic devices. The via level comprises at least one metal via that extends therethrough to electrically connect the first line level with the second line level. Further, the via level comprises at least one via-level metal wiring and/or electronic device.

摘要翻译： 本发明涉及包括通孔级布线和/或器件的集成电路。 具体而言，本发明的集成电路包括彼此间隔开的第一线路电平和第二线路电平，其间具有通路电平。 第一和第二线路级均包括金属布线和/或电子设备。 通孔级包括至少一个穿过其中的金属通孔，以将第一线路电平与第二线路电平电连接。 此外，通孔电平包括至少一个通孔级金属布线和/或电子器件。

公开(公告)号：US20070105354A1

公开(公告)日：2007-05-10

申请号：US11164108

申请日：2005-11-10

申请人： Douglas Coolbaugh ,  Xuefeng Liu ,  Robert Rassel ,  David Sheridan

发明人： Douglas Coolbaugh ,  Xuefeng Liu ,  Robert Rassel ,  David Sheridan

IPC分类号： H01L21/425

CPC分类号： H01L21/8249 ,  H01L29/0821 ,  H01L29/66272

摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.

摘要翻译： 一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。 特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。 该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比） 。 本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。

公开(公告)号：US20060270247A1

公开(公告)日：2006-11-30

申请号：US10908789

申请日：2005-05-26

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Kenneth Stein ,  Kunal Vaed

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Kenneth Stein ,  Kunal Vaed

IPC分类号： H01L21/336

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/45523 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/28194 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517

摘要： Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O2) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O3) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.

摘要翻译： 公开了形成高介电常数电介质层的方法，包括提供包括用于支撑衬底的保持器的处理室，引入包含高介电常数（Hi-K）电介质前体和氧（O 2） / SUB>）氧化剂进入处理室以形成衬底上的高介电常数电介质层的第一部分，并且从第一气体的流动切换到包括Hi-K电介质前体的第二气体的流动，以及 臭氧（O 3 3）氧化剂以形成第一部分上的高介电常数介电层的第二部分。 在替代实施例中，可以使用氧氧化剂在第二部分上形成另一部分。 本发明将产量提高了至少20％，而没有可靠性或泄漏降级，并且不需要额外的设备。

公开(公告)号：US20050093053A1

公开(公告)日：2005-05-05

申请号：US11001140

申请日：2004-12-02

申请人： Arne Ballantine ,  Douglas Coolbaugh ,  Jeffrey Gilbert ,  Joseph Greco ,  Glenn Miller

发明人： Arne Ballantine ,  Douglas Coolbaugh ,  Jeffrey Gilbert ,  Joseph Greco ,  Glenn Miller

IPC分类号： H01L29/73 ,  H01L21/314 ,  H01L21/318 ,  H01L21/328 ,  H01L21/331 ,  H01L29/08 ,  H01L31/11

CPC分类号： H01L29/66272 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/0804 ,  H01L29/0895

摘要： A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

公开(公告)号：US20050054171A1

公开(公告)日：2005-03-10

申请号：US10953378

申请日：2004-09-29

申请人： Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

发明人： Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US20070254449A1

公开(公告)日：2007-11-01

申请号：US11627408

申请日：2007-01-26

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Richard Rassel ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Richard Rassel ,  Robert Rassel

IPC分类号： H01L21/20

CPC分类号： H01L28/20

摘要： Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about the same TCRs.

摘要翻译： 整合在集成电路中的可调TCR电阻和制造可调TCR电阻的方法。 可调TCR电阻器包括具有相反极性和不同幅度TCR，相同极性和不同幅度TCR或具有相反极性和大约相同TCR的两种或更多种不同材料的两个或更多个电阻器。