公开(公告)号：US20150206564A1

公开(公告)日：2015-07-23

申请号：US14350997

申请日：2012-03-25

Applicant: Arijit Raychowdhury ,  David Kencke ,  Brian Doyle ,  Charles Kuo ,  James Tschanz ,  Fatih Hamzaoglu ,  Yih Wang ,  Roksana Golizadeh Mojarad

Inventor： Arijit Raychowdhury ,  David Kencke ,  Brian Doyle ,  Charles Kuo ,  James Tschanz ,  Fatih Hamzaoglu ,  Yih Wang ,  Roksana Golizadeh Mojarad

IPC: G11C11/16 ,  G11C5/12

CPC classification number: G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

Abstract: Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.

Abstract translation: 基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。 对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列 在BL上。 可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。 预充电的BL电容也可以用作电压积分器。

公开(公告)号：US08547777B2

公开(公告)日：2013-10-01

申请号：US12928989

申请日：2010-12-22

Applicant: Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

Inventor： Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/02

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08

Abstract: A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Abstract translation: 公开了一种用于在DRAM中选择字线驱动器的NOR架构。 用于选择最终字线驱动程序的低，中，高范围内单独解码的地址的完成。 字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

公开(公告)号：US08406073B1

公开(公告)日：2013-03-26

申请号：US12928948

申请日：2010-12-22

Applicant: Dinesh Somasekhar ,  Gunjan Pandya ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Balaji Srinivasan ,  Swaroop Ghosh ,  Meterelliyoz Mesut

Inventor： Dinesh Somasekhar ,  Gunjan Pandya ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Balaji Srinivasan ,  Swaroop Ghosh ,  Meterelliyoz Mesut

IPC: G11C8/00

CPC classification number: G11C11/4097 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094

Abstract: A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.

Abstract translation: 采用本地位线对和全局位线的分级DRAM感测装置和方法。 字线选择感测放大器群集中的单元，每个放大器与一对位线相关联。 选择本地位线之一用于耦合到全局位线和全局读出放大器。 集群位于形成一个存储体的多个子阵列中，其中全局位线从每个存储体延伸到全局读出放大器。

公开(公告)号：US20120163114A1

公开(公告)日：2012-06-28

申请号：US12928949

申请日：2010-12-22

Applicant: Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

Inventor： Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

IPC: G11C8/08

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4087

Abstract: A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Abstract translation: 公开了一种用于在DRAM中选择字线驱动器的NAND架构。 低，中，高范围的分离地址用于选择最终的字线驱动。 字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正。

公开(公告)号：US20110149666A1

公开(公告)日：2011-06-23

申请号：US12645623

申请日：2009-12-23

Applicant: Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang

Inventor： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C7/12 ,  G11C5/141 ,  G11C11/413

Abstract: Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

Abstract translation: 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。

公开(公告)号：US20070153610A1

公开(公告)日：2007-07-05

申请号：US11323361

申请日：2005-12-29

Applicant: Fatih Hamzaoglu ,  Kevin Zhang ,  Yih Wang

Inventor： Fatih Hamzaoglu ,  Kevin Zhang ,  Yih Wang

IPC: G11C5/14

CPC classification number: G11C5/146 ,  H03K19/0016

Abstract: For one disclosed embodiment, circuitry may bias one or more wells of a substrate from a first state to a second state. Bias by the circuitry of one or more wells of the substrate to the second state may be boosted. Other embodiments are also disclosed.

Abstract translation: 对于一个所公开的实施例，电路可以将衬底的一个或多个阱从第一状态偏置到第二状态。 通过衬底的一个或多个孔的电路到第二状态的偏置可以被提升。 还公开了其他实施例。

公开(公告)号：US06351156B1

公开(公告)日：2002-02-26

申请号：US09740104

申请日：2000-12-18

Applicant: Fatih Hamzaoglu ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek K. De

Inventor： Fatih Hamzaoglu ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek K. De

IPC: H03F345

CPC classification number: G11C7/02 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069

Abstract: A circuit and method for reducing noise in a memory circuit is disclosed. In one embodiment, the circuit includes an amplifier, a first transistor and a second transistor. The first transistor is capable of pulling up a first input port of the amplifier in response to a complement of the second memory signal. The second transistor is capable of pulling of a second input port of the amplifier in response to a complement of the first memory signal. In one embodiment, the method includes receiving a first memory signal at a first input port of an amplifier, receiving a second memory signal at a second input port of the amplifier, and pulling up the second input port in response to a complement of the first memory signal.

Abstract translation: 公开了一种用于降低存储器电路中的噪声的电路和方法。 在一个实施例中，电路包括放大器，第一晶体管和第二晶体管。 第一晶体管能够响应于第二存储器信号的补码而提升放大器的第一输入端口。 第二晶体管能够响应于第一存储器信号的补码而拉动放大器的第二输入端口。 在一个实施例中，该方法包括在放大器的第一输入端口处接收第一存储器信号，在放大器的第二输入端口接收第二存储器信号，以及响应于第一输入端口 记忆信号

公开(公告)号：US20250098179A1

公开(公告)日：2025-03-20

申请号：US18467984

申请日：2023-09-15

Applicant: Abhishek A. Sharma ,  Van H. Le ,  Fatih Hamzaoglu ,  Juan G. Alzate-Vinasco ,  Nikhil Jasvant Mehta ,  Vinaykumar Hadagali ,  Yu-Wen Huang ,  Honore Djieutedjeu ,  Tahir Ghani ,  Timothy Jen ,  Shailesh Kumar Madisetti ,  Jisoo Kim ,  Wilfred Gomes ,  Kamal Baloch ,  Vamsi Evani ,  Christopher Wiegand ,  James Pellegren ,  Sagar Suthram ,  Christopher M. Pelto ,  Gwang Soo Kim ,  Babita Dhayal ,  Prashant Majhi ,  Anand Iyer ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Pooya Tadayon ,  Nitin A. Deshpande

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Fatih Hamzaoglu ,  Juan G. Alzate-Vinasco ,  Nikhil Jasvant Mehta ,  Vinaykumar Hadagali ,  Yu-Wen Huang ,  Honore Djieutedjeu ,  Tahir Ghani ,  Timothy Jen ,  Shailesh Kumar Madisetti ,  Jisoo Kim ,  Wilfred Gomes ,  Kamal Baloch ,  Vamsi Evani ,  Christopher Wiegand ,  James Pellegren ,  Sagar Suthram ,  Christopher M. Pelto ,  Gwang Soo Kim ,  Babita Dhayal ,  Prashant Majhi ,  Anand Iyer ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Pooya Tadayon ,  Nitin A. Deshpande

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.

公开(公告)号：US20170047105A1

公开(公告)日：2017-02-16

申请号：US15062073

申请日：2016-03-05

Applicant: PULKIT JAIN ,  FATIH HAMZAOGLU ,  LIQIONG WEI

Inventor： PULKIT JAIN ,  FATIH HAMZAOGLU ,  LIQIONG WEI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659

Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.

Abstract translation: 描述了包括位线的装置。 该装置还包括耦合到位线的第一和第二存储单元。 第一存储单元具有第一存取晶体管。 第一存取晶体管耦合到第一线电阻。 第二存储单元具有第二存取晶体管。 第二存取晶体管耦合到第二线路电阻。 第二线电阻大于第一线电阻。 该装置还包括耦合到位线的第一和第二驱动器。 第二个驱动程序是比第一个驱动程序更强大的驱动程序。 该装置还包括选择第一驱动器以将信息写入第一存储单元并选择第二驱动器以将信息写入第二存储单元的电路。

公开(公告)号：US08982659B2

公开(公告)日：2015-03-17

申请号：US12645623

申请日：2009-12-23

Applicant: Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

Inventor： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

IPC: G11C5/14 ,  G11C7/12 ,  G11C11/413

CPC classification number: G11C7/12 ,  G11C5/141 ,  G11C11/413

Abstract: Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

Abstract translation: 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。