公开(公告)号：US20070205456A1

公开(公告)日：2007-09-06

申请号：US11711616

申请日：2007-02-28

Applicant: Myoung-Jae Lee ,  In-Kyeong Yoo ,  Eun-Hong Lee ,  Jong-Wan Kim ,  Dong-Chul Kim ,  Seung-Eon Ahn

Inventor： Myoung-Jae Lee ,  In-Kyeong Yoo ,  Eun-Hong Lee ,  Jong-Wan Kim ,  Dong-Chul Kim ,  Seung-Eon Ahn

IPC: H01L29/76

CPC classification number: H01L27/1021 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/73

Abstract: A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.

Abstract translation: 可以提供具有自身存在二极管特性的非易失性存储器件和/或包括非易失性存储器件的非易失性存储器阵列。 非易失性存储器件可以包括下电极，下电极上的第一半导体氧化物层，第一半导体氧化物层上的第二半导体氧化物层，和/或第二半导体氧化物层上的上电极。

公开(公告)号：US20060255392A1

公开(公告)日：2006-11-16

申请号：US11432620

申请日：2006-05-12

Applicant: Choong-Rae Cho ,  In-Kyeong Yoo ,  Yang-Kyu Choi ,  Sung-Il Cho

Inventor： Choong-Rae Cho ,  In-Kyeong Yoo ,  Yang-Kyu Choi ,  Sung-Il Cho

IPC: H01L29/94

CPC classification number: H01L49/003

Abstract: A transistor including a metal-insulation transition material and a method of manufacturing the same. The transistor including a metal-insulator transition material may include a substrate, a insulation layer formed on the substrate, a source region and a drain region separately formed from each other on the insulation layer, a tunneling barrier layer formed on at least one surface of the source region and the drain region, a metal-insulator transition material layer formed on the tunneling barrier layer and the insulation layer, a dielectric layer stacked on the metal-insulator transition material layer, and a gate electrode layer formed on the dielectric layer.

Abstract translation: 一种包括金属绝缘过渡材料的晶体管及其制造方法。 包括金属 - 绝缘体转移材料的晶体管可以包括基板，形成在基板上的绝缘层，在绝缘层上彼此分开形成的源极区域和漏极区域，形成在绝缘层的至少一个表面上的隧道势垒层 源极区域和漏极区域，形成在隧道势垒层和绝缘层上的金属 - 绝缘体转移材料层，堆叠在金属 - 绝缘体转移材料层上的电介质层和形成在电介质层上的栅极电极层。

公开(公告)号：US20060181220A1

公开(公告)日：2006-08-17

申请号：US11254793

申请日：2005-10-21

Applicant: Chang-wook Moon ,  In-kyeong Yoo

Inventor： Chang-wook Moon ,  In-kyeong Yoo

IPC: H01L21/00 ,  H01J7/24

CPC classification number: H01J9/025

Abstract: A method and apparatus for fabricating an emitter by colliding an arc with the surface of a wafer inside a vacuum chamber are provided. The apparatus includes: a vacuum chamber in which a wafer is inserted; a magnetic field generating unit for generating a uniform magnetic field inside the vacuum chamber; an electric field generating unit for forming an electric field parallel to the magnetic field inside the vacuum chamber; and a master emitter for emitting electrons towards the wafer. The electrons emitted from the master emitter move along the magnetic field and the electric field. The arc is generated when the electric field or the driving voltage surpasses a threshold by controlling the strength of the electric field and the driving voltage of the master emitter. Thus, the surface of the wafer is instantaneously melted and solidified by the arc, thereby forming the emitter with a sharp tip on the surface of the wafer.

Abstract translation: 提供了一种用于通过使电弧与真空室内的晶片的表面碰撞来制造发射器的方法和装置。 该装置包括：其中插入有晶片的真空室; 磁场产生单元，用于在真空室内产生均匀的磁场; 电场产生单元，用于形成与真空室内的磁场平行的电场; 以及用于向晶片发射电子的主发射器。 从主发射器发射的电子沿着磁场和电场移动。 当电场或驱动电压通过控制电场的强度和主发射极的驱动电压而超过阈值时，产生电弧。 因此，晶片的表面被电弧瞬间熔化和凝固，从而在晶片的表面上形成具有尖锐尖端的发射极。

公开(公告)号：US20060086966A1

公开(公告)日：2006-04-27

申请号：US11296510

申请日：2005-12-08

Applicant: In-kyeong Yoo ,  Byong-man Kim

Inventor： In-kyeong Yoo ,  Byong-man Kim

IPC: H01L29/76

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or the nonvolatile memory element is provided between the transistor and the substrate.

公开(公告)号：US07002841B2

公开(公告)日：2006-02-21

申请号：US10701436

申请日：2003-11-06

Applicant: In-Kyeong Yoo ,  Wan-jun Park

Inventor： In-Kyeong Yoo ,  Wan-jun Park

IPC: G11C11/34

CPC classification number: H01L27/226 ,  B82Y10/00 ,  G11C11/16

Abstract: An MRAM having improved integration density and ability to use a magnetic tunneling junction (MTJ) layer having a low MR ratio, and methods for manufacturing and driving the same, are disclosed. The MRAM includes a semiconductor substrate having a bipolar junction transistor (BJT) formed thereon, a bit line coupled to an emitter of the BJT, an MTJ layer coupled to the BJT, a word line coupled to the MTJ layer, a plate line coupled to the BJT so as to be spaced apart from the MTJ layer, and an interlayer dielectric formed between components of the MRAM, wherein the MTJ layer is coupled to a base and a collector of the BJT, the plate line is coupled to the collector, and an amplifying unit for amplifying a signal while data is read out from the MTJ layer is coupled to the bit line, thereby allowing precise reading of the data.

Abstract translation: 公开了具有改进的集成密度和使用具有低MR比的磁隧道结（MTJ）层的能力的MRAM及其制造和驱动方法。 MRAM包括其上形成有双极结型晶体管（BJT）的半导体衬底，耦合到BJT的发射极的位线，耦合到BJT的MTJ层，耦合到MTJ层的字线，耦合到 BJT与MTJ层间隔开，以及在MRAM的组件之间形成的层间电介质，其中MTJ层耦合到BJT的基极和集电极，板线耦合到集电器，并且 用于在从MTJ层读出数据时放大信号的放大单元被耦合到位线，从而允许精确地读取数据。

公开(公告)号：US06992923B2

公开(公告)日：2006-01-31

申请号：US11097157

申请日：2005-04-04

Applicant: Dong-wook Kim ,  In-kyeong Yoo ,  Jung-hyun Sok ,  June-key Lee

Inventor： Dong-wook Kim ,  In-kyeong Yoo ,  Jung-hyun Sok ,  June-key Lee

IPC: G11C11/00

CPC classification number: H01L27/228 ,  B82Y10/00

Abstract: A single transistor type magnetic random access memory device and a method of operating and manufacturing the same, wherein the single transistor type magnetic random access memory device includes a substrate, first and second doped regions spaced apart from each other, a gate dielectric layer on a portion of the semiconductor substrate between the first and second doped regions, a magnetic tunnel junction on the gate dielectric layer, word lines on the magnetic tunnel junction extending in a first direction which is the same direction as the second doped region, bit lines connected to the first doped region in a second direction perpendicular to the first direction, and an insulating layer covering the gate dielectric layer, the magnetic tunnel junction, and the word lines. The single transistor type magnetic random access memory device has a simple circuit structure, has a prolonged lifetime and is easy to manufacture.

公开(公告)号：US06953946B2

公开(公告)日：2005-10-11

申请号：US10674459

申请日：2003-10-01

Applicant: In-kyeong Yoo ,  Chang-wook Moon ,  Soo-hwan Jeong ,  Dong-wook Kim

Inventor： In-kyeong Yoo ,  Chang-wook Moon ,  Soo-hwan Jeong ,  Dong-wook Kim

IPC: G03F7/20 ,  H01J1/312 ,  H01J9/02 ,  H01J37/06 ,  H01J37/073 ,  H01J37/305 ,  H01L21/027 ,  H01L29/06 ,  H01L29/12 ,  H01L29/82 ,  H01L43/00

CPC classification number: B82Y10/00 ,  H01J1/312 ,  H01J9/022 ,  H01J9/027 ,  H01J2237/31774 ,  H01J2237/31783

Abstract: An emitter for an electron-beam projection lithography (EPL) system and a manufacturing method therefor are provided. The electron-beam emitter includes a substrate, an insulating layer overlying the substrate, and a gate electrode including a base layer formed on top of the insulating layer to a uniform thickness and an electron-beam blocking layer formed on the base layer in a predetermined pattern. The manufacturing method includes steps of: preparing a substrate; forming an insulating layer on the substrate; forming a base layer of a gate electrode by depositing a conductive metal on the insulating layer to a predetermined thickness; forming an electron-beam blocking layer of the gate electrode by depositing a metal capable of anodizing on the base layer to a predetermined thickness; and patterning the electron-beam blocking layer in a predetermined pattern by anodizing. The emitter provides a uniform electric field within the insulating layer and simplify the manufacturing method therefor.

Abstract translation: 提供了一种用于电子束投影光刻（EPL）系统的发射器及其制造方法。 电子束发射器包括衬底，覆盖衬底的绝缘层，以及包括形成在绝缘层顶部上的基底层至均匀厚度的栅极电极和以预定的方式形成在基底层上的电子束阻挡层 模式。 该制造方法包括以下步骤：制备衬底; 在所述基板上形成绝缘层; 通过在所述绝缘层上沉积导电金属至预定厚度来形成栅电极的基层; 通过在基底层上沉积能够阳极氧化的金属至预定的厚度来形成栅电极的电子束阻挡层; 并通过阳极氧化将预定图案中的电子束阻挡层图案化。 发射极在绝缘层内提供均匀的电场，并简化其制造方法。

公开(公告)号：US06913984B2

公开(公告)日：2005-07-05

申请号：US10743377

申请日：2003-12-23

Applicant: In-sook Kim ,  Sun-ae Seo ,  In-kyeong Yoo ,  Soo-hwan Jeong

Inventor： In-sook Kim ,  Sun-ae Seo ,  In-kyeong Yoo ,  Soo-hwan Jeong

IPC: B82B1/00 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/76

CPC classification number: B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  Y10S977/723 ,  Y10S977/774

Abstract: A method of fabricating memory with nano dots includes sequentially depositing a first insulating layer, a charge storage layer, a sacrificial layer, and a metal layer on a substrate in which source and drain electrodes are formed, forming a plurality of holes on the resultant structure by anodizing the metal layer and oxidizing portions of the sacrificial layer that are exposed through the holes, patterning the charge storage layer to have nano dots by removing the oxidized metal layer, and etching the sacrificial layer and the charge storage layer using the oxidized sacrificial layer as a mask, and removing the oxidized sacrificial layer, depositing a second insulating layer and a gate electrode on the patterned charge storage layer, and patterning the first insulating layer, the patterned charge storage layer, the second insulating layer, and the gate electrode to a predetermined shape, for forming memory having uniformly distributed nano-scale storage nodes.

Abstract translation: 利用纳米点制造存储器的方法包括在形成源极和漏极的衬底上依次沉积第一绝缘层，电荷存储层，牺牲层和金属层，在所得结构上形成多个孔 通过阳极氧化金属层并氧化通过孔露出的牺牲层的部分，通过去除氧化的金属层将电荷存储层图案化成具有纳米点，并且使用氧化的牺牲层蚀刻牺牲层和电荷存储层 作为掩模，并且去除氧化的牺牲层，在图案化的电荷存储层上沉积第二绝缘层和栅电极，并且将第一绝缘层，图案化电荷存储层，第二绝缘层和栅电极图案化，以 用于形成具有均匀分布的纳米级存储节点的存储器的预定形状。

公开(公告)号：US20050139882A1

公开(公告)日：2005-06-30

申请号：US11024469

申请日：2004-12-30

Applicant: Wenxu Xianyu ,  Takashi Noguchi ,  In-kyeong Yoo ,  Young-soo Park

Inventor： Wenxu Xianyu ,  Takashi Noguchi ,  In-kyeong Yoo ,  Young-soo Park

IPC: H01L21/3205 ,  G11C11/22 ,  H01L21/82 ,  H01L21/8239 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L31/119

CPC classification number: H01L27/11507 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/12

Abstract: In an electronic device, and a method of manufacturing the same, the electronic device includes a first substrate, a first lower capacitor on the first substrate, a first lower switching element on the first lower capacitor, and a second substrate on the first lower switching element. The electronic device may further include a second lower switching element which is isolated from the first lower capacitor, and an upper capacitor on the second substrate, the lower electrode of the upper capacitor being connected to the second lower switching element.

Abstract translation: 在电子设备及其制造方法中，电子设备包括第一基板，第一基板上的第一下部电容器，第一下部电容器上的第一下部开关元件，以及第一下部开关 元件。 电子设备还可以包括与第一下电容器隔离的第二下开关元件和第二基板上的上电容器，上电容器的下电极连接到第二下开关元件。

公开(公告)号：US06870173B2

公开(公告)日：2005-03-22

申请号：US10792849

申请日：2004-03-05

Applicant: Chang-wook Moon ,  In-kyeong Yoo ,  Dong-wook Kim

Inventor： Chang-wook Moon ,  In-kyeong Yoo ,  Dong-wook Kim

IPC: G21K1/093 ,  G03F7/20 ,  G03F7/207 ,  G21K5/04 ,  H01J37/305 ,  H01J37/317 ,  H01L21/027

CPC classification number: H01J37/3175 ,  B82Y10/00 ,  B82Y40/00 ,  H01J2237/0216 ,  H01J2237/15

Abstract: An electron-beam focusing apparatus for controlling a path of electron beams emitted from an electron-beam emitter in an electron-beam projection lithography (EPL) system includes top and bottom magnets for creating a magnetic field within a vacuum chamber, the top and bottom magnets disposed above and below the vacuum chamber into which a wafer is loaded, respectively; upper and lower pole pieces magnetically contacting the top and bottom magnets, respectively, the upper and lower pole pieces penetrating a top wall and a bottom wall of the vacuum chamber, respectively; and upper and lower projections having a circular shape, extending outwardly from facing surfaces of the upper and lower pole pieces, respectively.

Abstract translation: 用于控制电子束投影光刻（EPL）系统中从电子束发射器发射的电子束的路径的电子束聚焦装置包括用于在真空室内产生磁场的顶部和底部磁体，顶部和底部 分别设置在其上装载有晶片的真空室的上方和下方的磁体; 分别与顶部和底部磁体磁接触的上部和下部磁极件，上部和下部磁极片分别穿透真空室的顶壁和底壁; 以及分别具有圆形形状的上下突起，从上下极片的相对表面向外延伸。