公开(公告)号：US20120156855A1

公开(公告)日：2012-06-21

申请号：US13302080

申请日：2011-11-22

Applicant: Jae-Hwang SIM

Inventor： Jae-Hwang SIM

IPC: H01L21/76

CPC classification number: H01L29/788 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.

Abstract translation: 一种制造半导体器件的方法包括形成彼此间隔开第一距离的多个串，每个串包括在第二预栅结构之间间隔第二距离小于第一距离的第一预栅极结构，形成第一绝缘层 覆盖第一和第二预选栅极结构，形成绝缘层结构以填充串之间的空间，形成牺牲层图案以部分地填充第一和第二预选栅结构之间的空间，去除未覆盖的第一绝缘层的一部分 通过所述牺牲层图案以形成第一绝缘层图案，使未被所述第一绝缘层图案覆盖的所述第一和第二预选栅极结构的部分与导电层反应以形成栅极结构，并且在所述栅极结构上形成覆盖层 在门结构之间形成气隙。

公开(公告)号：US20120058639A1

公开(公告)日：2012-03-08

申请号：US13194229

申请日：2011-07-29

Applicant: Jae-Hwang SIM ,  Jong-Min LEE ,  Hojun SEONG

Inventor： Jae-Hwang SIM ,  Jong-Min LEE ,  Hojun SEONG

IPC: H01L21/283

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a nonvolatile memory device includes providing conductive pillars disposed in a first insulating layer and disposed on a semiconductor substrate, providing an etch stop layer on the first insulating layer, disposing a mold layer on the etch stop layer, and forming grooves in the mold layer. The grooves respectively extend over the conductive pillars in a first direction. The method further includes patterning the etch stop layer using the grooves to form holes respectively corresponding to the conductive pillars, and filling a metal into the grooves and the holes. The metal in the holes contacts the conductive pillars.

Abstract translation: 形成非易失性存储器件的方法包括提供设置在第一绝缘层中并设置在半导体衬底上的导电柱，在第一绝缘层上提供蚀刻停止层，在蚀刻停止层上设置模具层， 模具层。 凹槽分别在第一方向上延伸穿过导电柱。 该方法还包括使用凹槽图案化蚀刻停止层，以形成分别对应于导电柱的孔，并将金属填充到凹槽和孔中。 孔中的金属接触导电柱。

公开(公告)号：US08114778B2

公开(公告)日：2012-02-14

申请号：US12905318

申请日：2010-10-15

Applicant: Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-hwang Sim

Inventor： Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-hwang Sim

IPC: H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.

Abstract translation: 更具体地，涉及一种在半导体器件中形成微小图案的方法，更具体地，涉及通过双重图案形成在基底图案之间具有偶数个插入图案的半导体器件中的微小图案的方法，包括在第一基本图案和第二基底图案之间的插入图案 在半导体基板上横向分离的图案，其中交替地重复第一插入图案和第二插入图案以形成插入图案，该方法包括对与第二插入图案相邻的第二插入图案进行部分蚀刻的操作 第二基本图案或形成屏蔽层图案的操作，从而形成偶数个插入图案。

公开(公告)号：US20120007165A1

公开(公告)日：2012-01-12

申请号：US13181281

申请日：2011-07-12

Applicant: Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

Inventor： Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

IPC: H01L29/788 ,  H01L27/088

CPC classification number: H01L29/7881 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction.

Abstract translation: 半导体器件包括衬底，多个栅极结构，第一绝缘层间图案和第二绝缘层图案。 基板具有有源区域和场区域，有源区域和场区域中的每一个沿着第一方向延伸，并且有源区域和场区域在基本上垂直于第一方向的第二方向上交替地和重复地布置。 栅极结构在第一方向上彼此间隔开，每个栅极结构沿第二方向延伸。 第一绝缘层图案形成在每个栅极结构的侧壁的一部分上。 第二绝缘层图案覆盖栅极结构和第一绝缘层图案，并且在栅极结构之间具有沿第二方向延伸的空气通道的空气通道。

公开(公告)号：US08057692B2

公开(公告)日：2011-11-15

申请号：US12290420

申请日：2008-10-30

Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US20100327396A1

公开(公告)日：2010-12-30

申请号：US12824480

申请日：2010-06-28

Applicant: Yoon Moon Park ,  Jae Hwang Sim ,  Keon Soo Kim

Inventor： Yoon Moon Park ,  Jae Hwang Sim ,  Keon Soo Kim

IPC: H01L27/10 ,  H01L21/28

CPC classification number: H01L29/0657 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529

Abstract: A pattern structure for a semiconductor device includes a plurality of first patterns, each of the first patterns extending in a first direction in the shape of a line, neighboring first patterns being spaced apart from each other by a gap distance, the plurality of first patterns including a plurality of trenches in parallel with the line shapes, respective trenches being between neighboring first patterns, the plurality of trenches including long trenches and short trenches alternately arranged in a second direction substantially perpendicular to the first direction, and at least a second pattern, the second pattern being coplanar with the first pattern, end portions of the first patterns being connected to the second pattern.

Abstract translation: 用于半导体器件的图案结构包括多个第一图案，每个第一图案沿着第一方向延伸为线状，相邻的第一图案彼此间隔开间隔距离，多个第一图案 包括与所述线形平行的多个沟槽，相应的沟槽位于相邻的第一图案之间，所述多个沟槽包括沿基本上垂直于所述第一方向的第二方向交替布置的长沟槽和短沟槽，以及至少第二图案， 所述第二图案与所述第一图案共面，所述第一图案的端部连接到所述第二图案。

公开(公告)号：US20100221919A1

公开(公告)日：2010-09-02

申请号：US12653588

申请日：2009-12-16

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L21/302

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US20100155906A1

公开(公告)日：2010-06-24

申请号：US12573535

申请日：2009-10-05

Applicant: Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

Inventor： Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

IPC: H01L29/06

CPC classification number: H01L27/105 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526

Abstract: Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.

Abstract translation: 提供了一种通过在同时形成具有不同宽度的图案的同时在器件区域的一部分中进行双重图案化来形成图案密度加倍的半导体器件的图案的方法，以及具有该方法的结构的半导体器件 很容易适用。 半导体器件包括在第一方向上彼此平行延伸的多条线图案。 多个第一线图案在多个线条图案之间沿第二方向交替选择，并且每个第一线图案具有靠近第一侧的第一端。 在多个线图案之间沿第二方向交替地选择多个第二线图案，并且每个具有在第一侧附近存在的第二端。 第一线图案与第二线图案交替，并且每个第一线图案的第一端距离每第二线图案的第二端更远离第一侧。

公开(公告)号：US20090263749A1

公开(公告)日：2009-10-22

申请号：US12192430

申请日：2008-08-15

Applicant: Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

Inventor： Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

IPC: H01L21/302 ,  G03F7/20

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575

Abstract: A method of forming fine patterns of a semiconductor device, in which a plurality of conductive lines formed in a cell array region are integrally formed with contact pads for connecting the conductive lines to a peripheral circuit. In this method, a plurality of mold mask patterns, each including a first portion extending in a first direction and a second portion which is integrally formed with the first portion and extends in a second direction, are formed within a cell block on a substrate comprising a film which is to be etched. A first mask layer covering sidewalls and an upper surface of each of the plurality of mold mask patterns is formed on the substrate. First mask patterns are formed by partially removing the first mask layer so that a first area of the first mask layer remains and a second area of the first mask layer is removed. The first area of the first mask layer covers sidewalls of adjacent mold mask patterns from among the plurality of mold mask patterns by being located between the adjacent mold mask patterns, and the second area of the first mask layer covers portions of the sidewalls of the plurality of mold mask patterns, the portions corresponding to an outermost sidewall of a mold mask pattern block.

Abstract translation: 一种形成半导体器件的精细图案的方法，其中形成在单元阵列区域中的多个导线与用于将导线连接到外围电路的接触焊盘一体地形成。 在该方法中，在基板上形成多个模具掩模图案，每个模具掩模图案包括沿第一方向延伸的第一部分和与第一部分整体形成并沿第二方向延伸的第二部分， 要蚀刻的薄膜。 在基板上形成覆盖多个模具掩模图案中的每一个的侧壁和上表面的第一掩模层。 通过部分去除第一掩模层形成第一掩模图案，使得第一掩模层的第一区域保留，并且去除第一掩模层的第二区域。 第一掩模层的第一区域通过位于相邻的模具掩模图案之间而覆盖多个模具掩模图案中的相邻模具掩模图案的侧壁，并且第一掩模层的第二区域覆盖多个模具掩模图案的侧壁的部分 的模具掩模图案，其对应于模具掩模图案块的最外侧壁的部分。

公开(公告)号：US20090236651A1

公开(公告)日：2009-09-24

申请号：US12463545

申请日：2009-05-11

Applicant: Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

Inventor： Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

IPC: H01L27/105 ,  H01L29/788

CPC classification number: H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

Abstract translation: 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。