公开(公告)号：US20140087555A1

公开(公告)日：2014-03-27

申请号：US14091680

申请日：2013-11-27

Applicant: Yoonmoon PARK ,  Jae-Hwang SIM ,  Se-Young PARK ,  Keonsoo KIM ,  Jaehan LEE ,  Seungwon SEONG

Inventor： Yoonmoon PARK ,  Jae-Hwang SIM ,  Se-Young PARK ,  Keonsoo KIM ,  Jaehan LEE ,  Seungwon SEONG

IPC: H01L21/768

CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿透芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。

公开(公告)号：US20120299077A1

公开(公告)日：2012-11-29

申请号：US13412863

申请日：2012-03-06

Applicant: Jae-Hwang SIM ,  Jae-Bok Baek

Inventor： Jae-Hwang SIM ,  Jae-Bok Baek

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L21/28 ,  H01L21/28273 ,  H01L21/764 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/7881

Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.

Abstract translation: 半导体器件包括：衬底，包括第一区域和第二区域;栅极组，设置在衬底的第一区域中，栅极组包括多个单元栅极图案和至少一个选择栅极图案，第一栅极图案布置 在衬底的第二区域中，覆盖栅极组的顶表面和侧表面的组间隔件，具有第一拐点的组间隔件和覆盖第一栅极的顶表面和侧表面的第一图案间隔件 第一图案间隔物具有第二拐点。

公开(公告)号：US20160190004A1

公开(公告)日：2016-06-30

申请号：US14964624

申请日：2015-12-10

Applicant: Min-Sung Song ,  Jae-Hwang SIM ,  Joon-Sung LIM

Inventor： Min-Sung Song ,  Jae-Hwang SIM ,  Joon-Sung LIM

IPC: H01L21/768 ,  H01L21/027 ,  H01L27/115 ,  H01L21/311

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/11526

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Abstract translation: 本发明构思提供了制造半导体器件的方法和由其制造的半导体器件。 根据该方法，可以使用两个或三个光刻工艺和两个间隔物形成工艺来形成具有小于通过曝光工艺实现的最小间距的细间距的导电线。 此外，导线的节点分离区域可以容易地形成而没有错位问题。

公开(公告)号：US20150287644A1

公开(公告)日：2015-10-08

申请号：US14742981

申请日：2015-06-18

Applicant: Jae-Hwang SIM

Inventor： Jae-Hwang SIM

IPC: H01L21/8234

CPC classification number: H01L21/823437 ,  H01L21/823468 ,  H01L27/11521 ,  H01L29/66825

Abstract: A semiconductor device includes a substrate including an active region and a field region, first gate structures disposed on the active region, first air gaps disposed between the first gate structures, second gate structures disposed on the field region, second air gaps disposed between the second gate structures, and an interlayer insulating layer disposed on the first gate structures, the first air gaps, the second gate structures, and the second air gaps. A lowermost level of the second air gaps is lower than a lowermost level of the first gate structures.

Abstract translation: 半导体器件包括：衬底，其包括有源区和场区;布置在有源区上的第一栅极结构，设置在第一栅极结构之间的第一气隙，设置在场区上的第二栅极结构， 栅极结构和设置在第一栅极结构，第一气隙，第二栅极结构和第二气隙上的层间绝缘层。 第二气隙的最低水平低于第一门结构的最低水平。

公开(公告)号：US20080096377A1

公开(公告)日：2008-04-24

申请号：US11623269

申请日：2007-01-15

Applicant: Dong-Hwa KWAK ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Jin-Ho KIM ,  Ki-Nam KIM

Inventor： Dong-Hwa KWAK ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Jin-Ho KIM ,  Ki-Nam KIM

IPC: H01L21/44

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

Abstract: In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.

Abstract translation: 在一个实施例中，半导体器件包括奇数触点和相应的奇数行。 间隔物形成在奇数行的侧壁上，并且通过执行蚀刻工艺形成均匀线的均匀开口。 偶数触点形成在均匀开口中，然后形成均匀的线。

公开(公告)号：US20120252185A1

公开(公告)日：2012-10-04

申请号：US13470773

申请日：2012-05-14

Applicant: Young-Ho LEE ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Sang-Yong PARK

Inventor： Young-Ho LEE ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Sang-Yong PARK

IPC: H01L21/762 ,  H01L21/302 ,  H01L21/28

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。 间隔件形成在第一和第二掩模结构的相对侧壁上。 第一掩模结构被选择性地从第一区域中的间隔物之间​​移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案 在第二区域中。

公开(公告)号：US20120156855A1

公开(公告)日：2012-06-21

申请号：US13302080

申请日：2011-11-22

Applicant: Jae-Hwang SIM

Inventor： Jae-Hwang SIM

IPC: H01L21/76

CPC classification number: H01L29/788 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.

Abstract translation: 一种制造半导体器件的方法包括形成彼此间隔开第一距离的多个串，每个串包括在第二预栅结构之间间隔第二距离小于第一距离的第一预栅极结构，形成第一绝缘层 覆盖第一和第二预选栅极结构，形成绝缘层结构以填充串之间的空间，形成牺牲层图案以部分地填充第一和第二预选栅结构之间的空间，去除未覆盖的第一绝缘层的一部分 通过所述牺牲层图案以形成第一绝缘层图案，使未被所述第一绝缘层图案覆盖的所述第一和第二预选栅极结构的部分与导电层反应以形成栅极结构，并且在所述栅极结构上形成覆盖层 在门结构之间形成气隙。

公开(公告)号：US20120058639A1

公开(公告)日：2012-03-08

申请号：US13194229

申请日：2011-07-29

Applicant: Jae-Hwang SIM ,  Jong-Min LEE ,  Hojun SEONG

Inventor： Jae-Hwang SIM ,  Jong-Min LEE ,  Hojun SEONG

IPC: H01L21/283

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a nonvolatile memory device includes providing conductive pillars disposed in a first insulating layer and disposed on a semiconductor substrate, providing an etch stop layer on the first insulating layer, disposing a mold layer on the etch stop layer, and forming grooves in the mold layer. The grooves respectively extend over the conductive pillars in a first direction. The method further includes patterning the etch stop layer using the grooves to form holes respectively corresponding to the conductive pillars, and filling a metal into the grooves and the holes. The metal in the holes contacts the conductive pillars.

Abstract translation: 形成非易失性存储器件的方法包括提供设置在第一绝缘层中并设置在半导体衬底上的导电柱，在第一绝缘层上提供蚀刻停止层，在蚀刻停止层上设置模具层， 模具层。 凹槽分别在第一方向上延伸穿过导电柱。 该方法还包括使用凹槽图案化蚀刻停止层，以形成分别对应于导电柱的孔，并将金属填充到凹槽和孔中。 孔中的金属接触导电柱。

公开(公告)号：US20120007165A1

公开(公告)日：2012-01-12

申请号：US13181281

申请日：2011-07-12

Applicant: Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

Inventor： Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

IPC: H01L29/788 ,  H01L27/088

CPC classification number: H01L29/7881 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction.

Abstract translation: 半导体器件包括衬底，多个栅极结构，第一绝缘层间图案和第二绝缘层图案。 基板具有有源区域和场区域，有源区域和场区域中的每一个沿着第一方向延伸，并且有源区域和场区域在基本上垂直于第一方向的第二方向上交替地和重复地布置。 栅极结构在第一方向上彼此间隔开，每个栅极结构沿第二方向延伸。 第一绝缘层图案形成在每个栅极结构的侧壁的一部分上。 第二绝缘层图案覆盖栅极结构和第一绝缘层图案，并且在栅极结构之间具有沿第二方向延伸的空气通道的空气通道。

公开(公告)号：US20080096391A1

公开(公告)日：2008-04-24

申请号：US11871877

申请日：2007-10-12

Applicant: Sung-Hyun KWON ,  Jae-Hwang SIM ,  Dong-Hwa KWAK ,  Joo-Young KIM

Inventor： Sung-Hyun KWON ,  Jae-Hwang SIM ,  Dong-Hwa KWAK ,  Joo-Young KIM

IPC: H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A method for fabricating a semiconductor device having fine contact holes is exemplary disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.

Abstract translation: 公开了一种制造具有精细接触孔的半导体器件的方法。 该方法包括在半导体衬底上形成限定有源区的隔离层。 在具有隔离层的半导体衬底上形成层间电介质层。 在层间电介质层上形成第一成型图案。 还形成了位于第一模制图案之间并与之间隔开的第二模制图案。 形成围绕第一和第二模制图案的侧壁的掩模图案。 通过去除第一和第二模制图案形成开口。 通过使用掩模图案作为蚀刻掩模蚀刻层间电介质层来形成接触孔。