公开(公告)号：US20150006805A1

公开(公告)日：2015-01-01

申请号：US13931701

申请日：2013-06-28

Applicant: DANNIE G. FEEKES ,  SHLOMO RAIKIN ,  BLAISE FANNING ,  JOYDEEP RAY ,  JULIUS MANDELBLAT ,  ARIEL BERKOVITS ,  ERAN SHIFER ,  ZVIKA GREENFIELD ,  EVGENY BOLOTIN

Inventor： DANNIE G. FEEKES ,  SHLOMO RAIKIN ,  BLAISE FANNING ,  JOYDEEP RAY ,  JULIUS MANDELBLAT ,  ARIEL BERKOVITS ,  ERAN SHIFER ,  ZVIKA GREENFIELD ,  EVGENY BOLOTIN

IPC: G06F3/06

CPC classification number: G06F12/0893 ,  G06F1/32 ,  G06F1/3275 ,  G06F12/063 ,  G06F12/08 ,  G06F12/0866 ,  G06F2212/205 ,  G06F2212/206 ,  G06F2212/281 ,  G06F2212/604 ,  G06F2212/608 ,  Y02D10/13 ,  Y02D10/14

Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Abstract translation: 描述了混合多层存储器架构技术。 片上系统（SOC）包括多个功能单元和耦合到功能单元的多级存储器控制器（MLMC）。 MLMC耦合到混合多级存储器架构，其包括位于SOC的封装上的第一级动态随机存取存储器（近似存储器）和位于该存储器的二级DRAM（远存储器））的混合多级存储器架构 SOC的脱离包装。 MLMC将第一级DRAM和第二级DRAM作为连续可寻址存储空间，并将第一级DRAM提供给软件，作为第二级DRAM存储容量的附加存储容量。 第一级DRAM不存储二级DRAM的内容副本。

公开(公告)号：US20120095607A1

公开(公告)日：2012-04-19

申请号：US13335638

申请日：2011-12-22

Applicant: Ryan D. Wells ,  Avinash N. Ananthakrishnan ,  Inder Sodhi ,  Eric C. Samson ,  Joydeep Ray

Inventor： Ryan D. Wells ,  Avinash N. Ananthakrishnan ,  Inder Sodhi ,  Eric C. Samson ,  Joydeep Ray

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3253 ,  Y02D10/151

Abstract: According to one embodiment of the invention, an integrated circuit device comprises an interconnect, at least one compute engine and a control unit. Coupled to the at least one compute engine via the interconnect, the control unit to analyze heuristic information from the at least one compute engine and to increase or decrease a bandwidth of the interconnect based on the heuristic information.

Abstract translation: 根据本发明的一个实施例，集成电路设备包括互连，至少一个计算引擎和控制单元。 所述控制单元经由所述互连耦合到所述至少一个计算引擎，以分析来自所述至少一个计算引擎的启发式信息，并且基于所述启发式信息来增加或减少所述互连的带宽。

公开(公告)号：US10649956B2

公开(公告)日：2020-05-12

申请号：US15477027

申请日：2017-04-01

Applicant: Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

Inventor： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC: G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/0831

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180308201A1

公开(公告)日：2018-10-25

申请号：US15494905

申请日：2017-04-24

Applicant: Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

Inventor： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06F9/46 ,  G06N3/063 ,  G06T15/005 ,  G06T15/04 ,  G09G5/363

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.

公开(公告)号：US20180300840A1

公开(公告)日：2018-10-18

申请号：US15488632

申请日：2017-04-17

Applicant: Joydeep Ray ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Travis T. Schluessler ,  Linda L. Hurd ,  Eric J. Hoekstra

Inventor： Joydeep Ray ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Travis T. Schluessler ,  Linda L. Hurd ,  Eric J. Hoekstra

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60 ,  G09G5/39 ,  G09G5/00

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to render data from an application to be displayed on a display panel, and a memory to store the compressed final display surface writes. The processor is to compress final display surface writes of the data to be displayed on the display panel in a format to be displayed on the display to allow a display engine coupled to the display to stream the compressed final display surface writes to the display.

公开(公告)号：US20180300238A1

公开(公告)日：2018-10-18

申请号：US15488637

申请日：2017-04-17

Applicant: Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

Inventor： Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC: G06F12/06

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

公开(公告)号：US20180285120A1

公开(公告)日：2018-10-04

申请号：US15477030

申请日：2017-04-01

Applicant: Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan Bhairavabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan Bhairavabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G06F9/38 ,  G06F9/345 ,  G06F9/30 ,  G06F12/084 ,  G06T1/60 ,  G06T1/20 ,  G09G5/36

CPC classification number: G09G5/363 ,  G06F9/461 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/455 ,  G09G5/001 ,  G09G2340/02 ,  G09G2350/00 ,  G09G2352/00 ,  G09G2360/08 ,  G09G2360/121

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US20220334982A1

公开(公告)日：2022-10-20

申请号：US17827556

申请日：2022-05-27

Applicant: NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

Inventor： NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

IPC: G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20180301119A1

公开(公告)日：2018-10-18

申请号：US15488662

申请日：2017-04-17

Applicant: Altug Koker ,  Abhishek R. Appu ,  Bhushan M. Borole ,  Wenyin Fu ,  Kamal Sinha ,  Joydeep Ray

Inventor： Altug Koker ,  Abhishek R. Appu ,  Bhushan M. Borole ,  Wenyin Fu ,  Kamal Sinha ,  Joydeep Ray

IPC: G09G5/36

CPC classification number: G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G09G5/366 ,  G09G2310/066 ,  G09G2310/08 ,  G09G2340/02 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2370/022 ,  G09G2370/16

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

公开(公告)号：US20180293185A1

公开(公告)日：2018-10-11

申请号：US15482666

申请日：2017-04-07

Applicant: BALAJI VEMBU ,  ALTUG KOKER ,  JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  NIRANJAN L. COORAY

Inventor： BALAJI VEMBU ,  ALTUG KOKER ,  JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  NIRANJAN L. COORAY

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/1045 ,  G06F13/40

Abstract: An apparatus and method for dynamic provisioning and traffic control on a memory fabric. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated set of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment; and a plurality of queues associated with each VM at different levels of a memory interconnection fabric, the queues for a first VM to store memory traffic for that VM at the different levels of the memory interconnection fabric; arbitration hardware logic coupled to the plurality of queues and distributed across the different levels of the memory interconnection fabric, the arbitration hardware logic to cause memory traffic to be blocked from one or more upstream queues of the first VM upon detecting that a downstream queue associated with the first VM is full or at a specified threshold.