公开(公告)号：US07498205B2

公开(公告)日：2009-03-03

申请号：US11524404

申请日：2006-09-21

Applicant: Hoe Ku Jung ,  Myung Sam Kang ,  Jung Hyun Park

Inventor： Hoe Ku Jung ,  Myung Sam Kang ,  Jung Hyun Park

IPC: H01L21/00

CPC classification number: H05K3/4652 ,  H01L21/481 ,  H01L23/13 ,  H01L23/49805 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K3/4697 ,  H05K2203/0769 ,  H05K2203/308 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for manufacturing a substrate having a cavity which includes forming a barrier around a predetermined area where the cavity is to be formed on a copper foil laminated master, an internal circuit formed in the copper foil laminated master; coating a thermosetting material in the area where the cavity is to be formed; laminating a dielectric layer and a copper foil layer on the copper foil laminated master, on which the thermosetting material is coated; pressing the laminated dielectric layer and copper foil layer using a press plate, on which a protruded part is formed in an area corresponding to the area where the cavity is to be formed; forming an external circuit pattern in the upper part of the laminated dielectric layer; and dissolving the coated thermosetting material using a solvent and forming the cavity.

Abstract translation: 一种用于制造具有空腔的基板的方法，所述基板包括在铜箔层压母版上形成空腔周围的预定区域周围的阻挡层，形成在铜箔层压母板中的内部电路; 在要形成空腔的区域中涂覆热固性材料; 在铜箔层压母版上层叠电介质层和铜箔层，涂覆热固性材料; 使用压板对叠层电介质层和铜箔层进行压制，在其上形成有与要形成空腔的区域相对应的区域中的突出部分; 在叠层电介质层的上部形成外部电路图案; 并使用溶剂溶解涂覆的热固性材料并形成空腔。

公开(公告)号：US20080102410A1

公开(公告)日：2008-05-01

申请号：US11976211

申请日：2007-10-22

Applicant: Ji-Eun Kim ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Jeong-Woo Park ,  Sang-Duck Kim

Inventor： Ji-Eun Kim ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Jeong-Woo Park ,  Sang-Duck Kim

IPC: G03C5/00

CPC classification number: H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/183 ,  H05K3/108 ,  H05K3/20 ,  H05K3/4658 ,  H05K3/4697 ,  H05K2203/308 ,  H01L2224/0401

Abstract: A method of manufacturing a printed circuit board is disclosed, in which a cavity is formed for embedding a component, which includes: providing a core board, in which an inner circuit is buried; forming a first via in the core board for interlayer conduction; selectively forming a first photoresist in a position on the core board in correspondence with a position of the cavity; stacking a first build-up layer, on which a first outer circuit is formed, on the core board; and selectively removing the first build-up layer in correspondence with the position of the cavity and removing the first photoresist. Utilizing the method, a board can be manufactured with greater precision, as the thickness tolerance of the cavity may be obtained by controlling the thickness of the photoresist, and the overall thickness of the board can be controlled by controlling the height of the cavity.

Abstract translation: 公开了一种制造印刷电路板的方法，其中形成用于嵌入部件的空腔，其包括：提供其中埋入内部电路的芯板; 在芯板中形成层间导电的第一通孔; 在所述芯板上与所述腔的位置对应地选择性地形成第一光致抗蚀剂; 在芯板上堆叠形成有第一外部电路的第一堆积层; 并且与空腔的位置相对应地选择性地去除第一堆积层并除去第一光致抗蚀剂。 利用该方法，可以通过控制光致抗蚀剂的厚度来获得更高精度的板，因为通过控制光致抗蚀剂的厚度可以获得空腔的厚度公差，并且可以通过控制空腔的高度来控制板的整体厚度。

公开(公告)号：US20080031990A1

公开(公告)日：2008-02-07

申请号：US11726704

申请日：2007-03-22

Applicant: Myung Sung Woo ,  Dong Yeon Jung ,  Sung Ho Han ,  Yun Hyng Lee ,  Jung Hyun Park

Inventor： Myung Sung Woo ,  Dong Yeon Jung ,  Sung Ho Han ,  Yun Hyng Lee ,  Jung Hyun Park

IPC: B30B11/00

CPC classification number: C03B11/08 ,  C03B11/005 ,  C03B11/122 ,  C03B11/125 ,  C03B11/16 ,  C03B2215/49 ,  C03B2215/80 ,  C03B2215/86 ,  Y02P40/57 ,  Y10S425/808

Abstract: Disclosed herein is an apparatus for manufacturing a megapixel multi-focus lens. The lens manufacturing apparatus of the present invention includes a loading means for supplying a mold body, in which a blank, interposed between upper and lower molds, is placed, to a forming position, a compression-forming means, which preheats, compresses and cools the supplied mold body such that the blank is formed into a multi-focus lens having an aspherical surface, and a discharge means, which discharges the multi-focus lens formed by the compression-forming means. Therefore, processes from loading to discharging can be automated, so that the productivity of the apparatus for manufacturing the multi-focus lens can be markedly enhanced. Furthermore, because the lens manufacturing apparatus is covered with a cabinet, a superior appearance thereof is ensured. In addition, because various electric components for controlling the compression-forming means are provided in the cabinet, it is not necessary to separately install electrical control parts for mechanical parts.

Abstract translation: 本文公开了一种用于制造百万像素多焦点透镜的装置。 本发明的透镜制造装置包括：用于供给模具主体的装载装置，在模具主体中，将设置在上模和下模之间的坯料放置到成形位置，预压，压缩和冷却的压缩成形装置 提供的模具体使得坯料形成为具有非球面的多焦点透镜，以及排出由压缩成形装置形成的多焦点透镜的放电装置。 因此，从加载到放电的过程可以自动化，从而可以显着提高用于制造多焦点透镜的装置的生产率。 此外，由于透镜制造装置被机壳覆盖，因此确保了其优良的外观。 此外，由于在机壳中设置用于控制压缩成形装置的各种电气部件，因此不需要分别安装用于机械部件的电气控制部件。

公开(公告)号：USD560627S1

公开(公告)日：2008-01-29

申请号：US29269993

申请日：2006-12-12

Applicant: Jung-Hyun Park ,  Hyun-Teak Lim ,  Min-Ho Cha

Designer： Jung-Hyun Park ,  Hyun-Teak Lim ,  Min-Ho Cha

公开(公告)号：USD560182S1

公开(公告)日：2008-01-22

申请号：US29269994

申请日：2006-12-12

Applicant: Jung-Hyun Park

Designer： Jung-Hyun Park

公开(公告)号：USD541811S1

公开(公告)日：2007-05-01

申请号：US29241720

申请日：2005-10-31

Applicant: Jung-Hyun Park

Designer： Jung-Hyun Park

公开(公告)号：US20070065988A1

公开(公告)日：2007-03-22

申请号：US11524403

申请日：2006-09-21

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H01L21/00

CPC classification number: H05K3/4652 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/4697 ,  H05K2201/09536 ,  H05K2203/0191 ,  H05K2203/063 ,  H05K2203/308 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit patter on both sides of a seed layer by use of a first dry film, the seed layer being for forming a circuit pattern on both sides; (b) laminating a second dry film on the first dry film on both sides of the seed layer, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed on both sides of the seed layer, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method for manufacturing a substrate with a cavity in accordance with the present invention can improve the efficiency of a substrate manufacturing process by using both sides of a seed layer to manufacture the substrate with a cavity.

Abstract translation: 公开了一种用于制造具有空腔的衬底的方法。 该方法包括：（a）通过使用第一干膜在种子层的两侧形成第一电路图案，种子层用于在两侧形成电路图案; （b）在种子层两侧的第一干膜上层叠第二干膜，第二干膜的厚度对应于待形成的空腔的深度; （c）在种子层的两侧上在要形成空腔的区域之外的区域层叠电介质层，电介质层的厚度对应于待形成的空腔的深度; （d）在种子层上层叠具有第二电路图案的铜箔层叠主板; 和（e）通过在去除种子层之后剥离第一干膜和第二干膜来形成空腔。 根据本发明的用于制造具有空腔的基板的方法可以通过使用种子层的两面来制造具有空腔的基板来提高基板制造工艺的效率。

公开(公告)号：US20070026651A1

公开(公告)日：2007-02-01

申请号：US11480380

申请日：2006-07-05

Applicant: Hun-Hyeoung Leam ,  Hyeon-Deok Lee ,  Young-Sub You ,  Won-Jun Jang ,  Woong Lee ,  Jung-Hyun Park ,  Sang-Kyoung Lee ,  Jung-Geun Jee ,  Sang-Hoon Lee

Inventor： Hun-Hyeoung Leam ,  Hyeon-Deok Lee ,  Young-Sub You ,  Won-Jun Jang ,  Woong Lee ,  Jung-Hyun Park ,  Sang-Kyoung Lee ,  Jung-Geun Jee ,  Sang-Hoon Lee

IPC: H01L21/38

CPC classification number: H01L21/28273 ,  H01L21/32115 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.

Abstract translation: 在制造诸如闪速存储器件的半导体器件的方法中，形成具有开口的绝缘图案以部分地暴露衬底的表面。 第一硅层形成在基板的露出表面部分和绝缘图案上。 第一硅层具有覆盖衬底的先前暴露部分的开口接缝。 在足以诱导硅迁移的温度下进行在基板上的热处理，以便通过硅迁移使开放的接缝闭合。 然后在第一硅层上形成第二硅层。 因此，可以提高从第一和第二硅层获得的浮栅的表面轮廓。

公开(公告)号：USD530694S1

公开(公告)日：2006-10-24

申请号：US29241719

申请日：2005-10-31

Applicant: Jung-Hyun Park

Designer： Jung-Hyun Park

公开(公告)号：US20060145719A1

公开(公告)日：2006-07-06

申请号：US11325145

申请日：2006-01-03

Applicant: Hyeck-Jin Jeong ,  Jung-Hyun Park ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Seok-Young Yoon

Inventor： Hyeck-Jin Jeong ,  Jung-Hyun Park ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Seok-Young Yoon

IPC: G01R31/02

CPC classification number: G01R1/0466 ,  G01R1/0483 ,  G01R1/06722

Abstract: A POGO pin that can measure low frequency products as well as RF products and also have a long life span, and a test socket including the POGO pin are provided. The POGO pin includes a metal plunger formed of a conductive metal so as to electrically contact the semiconductor package, and a rubber contact pin connected with the metal plunger and formed of a conductive rubber so as to electrically contact the test board.

Abstract translation: 一个POGO引脚，可以测量低频产品以及RF产品，并且具有较长的使用寿命，并提供包含POGO引脚的测试插座。 POGO针包括由导电金属形成的金属柱塞，以与半导体封装件电接触;以及橡胶触针，与金属柱塞连接并由导电橡胶形成，以便电接触测试板。