公开(公告)号：US08124880B2

公开(公告)日：2012-02-28

申请号：US11976207

申请日：2007-10-22

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/03

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US20110221074A1

公开(公告)日：2011-09-15

申请号：US13067219

申请日：2011-05-17

Applicant: Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L23/488

CPC classification number: H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A board on chip package including a photo solder resist having a cavity and a pattern on one side, the pattern corresponding to a circuit wire; a solder ball pad accommodated in the cavity; a circuit wire electrically connected with the solder ball pad, and formed on the other side of the photo solder resist; a semiconductor chip mounted on the solder ball pad by a flip chip bonding; and a passivation material to mold the semiconductor chip.

Abstract translation: 一种片上封装，包括具有空腔和一侧图案的光阻焊剂，该图案对应于电路线; 容纳在腔中的焊球垫; 与焊锡球焊盘电连接并形成在光阻焊剂的另一侧上的电路线; 通过倒装芯片焊接安装在焊球垫上的半导体芯片; 以及用于模制半导体芯片的钝化材料。

公开(公告)号：US07562446B2

公开(公告)日：2009-07-21

申请号：US11524403

申请日：2006-09-21

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/4652 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/4697 ,  H05K2201/09536 ,  H05K2203/0191 ,  H05K2203/063 ,  H05K2203/308 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit patter on both sides of a seed layer by use of a first dry film, the seed layer being for forming a circuit pattern on both sides; (b) laminating a second dry film on the first dry film on both sides of the seed layer, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed on both sides of the seed layer, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method for manufacturing a substrate with a cavity in accordance with the present invention can improve the efficiency of a substrate manufacturing process by using both sides of a seed layer to manufacture the substrate with a cavity.

Abstract translation: 公开了一种用于制造具有空腔的衬底的方法。 该方法包括：（a）通过使用第一干膜在种子层的两侧形成第一电路图案，种子层用于在两侧形成电路图案; （b）在种子层两侧的第一干膜上层叠第二干膜，第二干膜的厚度对应于待形成的空腔的深度; （c）在种子层的两侧上在要形成空腔的区域之外的区域层叠电介质层，电介质层的厚度对应于待形成的空腔的深度; （d）在种子层上层叠具有第二电路图案的铜箔层叠主板; 和（e）通过在去除种子层之后剥离第一干膜和第二干膜来形成空腔。 根据本发明的用于制造具有空腔的基板的方法可以通过使用种子层的两面来制造具有空腔的基板来提高基板制造工艺的效率。

公开(公告)号：US20080098597A1

公开(公告)日：2008-05-01

申请号：US11976072

申请日：2007-10-19

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K3/02

CPC classification number: H05K3/20 ,  H05K3/0058 ,  H05K3/108 ,  H05K3/4611 ,  H05K3/4682 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of manufacturing a circuit board is disclosed. A method of manufacturing a circuit board that includes forming a first circuit pattern on the insulation layer of a carrier, in which an insulation layer and a first seed layer are stacked in order; stacking and pressing the carrier and an insulation board with the side of the carrier having the first circuit pattern facing the insulation board; removing the carrier to transfer the first circuit pattern and the insulation layer onto the insulation board; and forming a second circuit pattern on the insulation layer transferred to the insulation board, allows fine pitch circuit patterns to enable the manufacture of fine circuit patterns of high density on the board, and allows the manufacture of a multi-layer circuit board with a simple process.

Abstract translation: 公开了一种制造电路板的方法。 一种制造电路板的方法，包括在载体的绝缘层上形成第一电路图案，其中绝缘层和第一种子层依次层叠; 堆叠并按压载体和绝缘板，其中载体侧具有面向绝缘板的第一电路图案; 移除载体以将第一电路图案和绝缘层转移到绝缘板上; 并且在转移到绝缘板的绝缘层上形成第二电路图案，允许精细的间距电路图案能够在板上制造高密度的精细电路图案，并且允许制造具有简单的多层电路板 处理。

公开(公告)号：US20070065986A1

公开(公告)日：2007-03-22

申请号：US11524402

申请日：2006-09-21

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H01L21/00

CPC classification number: H05K3/4652 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/183 ,  H05K3/205 ,  H05K3/4697 ,  H05K2201/09536 ,  H05K2203/0574 ,  H05K2203/063 ,  H05K2203/308 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method in accordance with the present invention can mount a plurality of integrated circuits by reducing the thickness of a substrate on a package on package.

Abstract translation: 公开了一种用于制造具有空腔的衬底的方法。 该方法包括：（a）通过使用第一干膜在种子层的一侧上形成第一电路图案; （b）在第一干膜上层压第二干膜，第二干膜的厚度对应于待形成的空腔的深度; （c）在要形成空腔的区域外的区域上层叠电介质层，所述电介质层的厚度对应于待形成的空腔的深度; （d）在种子层上层叠具有第二电路图案的铜箔层叠主板; 和（e）通过在去除种子层之后剥离第一干膜和第二干膜来形成空腔。 根据本发明的方法可以通过减小封装上的封装上的衬底的厚度来安装多个集成电路。

公开(公告)号：US20100255634A1

公开(公告)日：2010-10-07

申请号：US12801574

申请日：2010-06-15

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L21/60 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A manufacturing method of bottom substrate of package. A bottom substrate of a package on package electrically connected to a top substrate by means of a solder ball, including a core board, a solder ball pad formed on a surface of the core board in correspondence with a location of the solder ball, an insulation layer laminated on the core board, a through hole formed by removing a part of the insulation layer such that the solder ball pad is exposed, and a metallic layer filled in the through hole and connected electrically with the solder ball, allows the number of ICs mounted on a bottom substrate to be increased without increasing the size of a solder ball, and allows the size and pitch of the solder balls to be made smaller by controlling the thickness of the insulation layer laminated on the bottom substrate, whereby more signal transmission is possible between a top substrate and a bottom substrate.

Abstract translation: 封装底部基板的制造方法。 封装的封装的底部衬底通过焊球电连接到顶部衬底，所述焊球包括芯板，与所述焊球的位置对应地形成在所述芯板的表面上的焊球焊盘，绝缘体 层叠在芯板上的通孔，通过去除绝缘层的一部分使得焊球焊盘露出而形成的通孔以及填充在通孔中并与焊球电连接的金属层允许IC的数量 安装在底部基板上以增加焊球的尺寸，并且通过控制层叠在底部基板上的绝缘层的厚度，可以使焊球的尺寸和间距变小，由此更多的信号传输是 可能在顶部基板和底部基板之间。

公开(公告)号：US07802358B2

公开(公告)日：2010-09-28

申请号：US12453832

申请日：2009-05-22

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H05K3/00

CPC classification number: H05K3/4691 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K1/189 ,  H05K3/4623 ,  H05K2201/055 ,  H05K2201/09536 ,  H05K2201/10515 ,  H05K2203/049 ,  H05K2203/063 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A manufacturing method for rigid-flexible multi-layer printed circuit board including: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. When the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.

Abstract translation: 一种刚性柔性多层印刷电路板的制造方法，包括：柔性基板，其两侧形成有可弯曲的电路; 层叠在柔性基板上的刚性基板和电路形成在两侧，并且形成有安装半导体芯片的空腔; 以及粘合柔性基板和刚性基板并具有绝缘性的粘合片。 当安装相同数量的半导体芯片或实施POP时，封装的整体厚度可以更低。 此外，可以使用空间作为芯层的厚度来安装另外两个半导体芯片，并且可以实现当传统技术中安装在底部基板上的半导体芯片的数量变为二倍时的结构是不可能的。

公开(公告)号：US20080264676A1

公开(公告)日：2008-10-30

申请号：US11976207

申请日：2007-10-22

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/00

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US20080009128A1

公开(公告)日：2008-01-10

申请号：US11708339

申请日：2007-02-21

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L21/44

CPC classification number: H05K3/205 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2203/0733 ,  H05K2203/1572

Abstract: A buried pattern substrate and a manufacturing method thereof are disclosed. A method of manufacturing a buried pattern substrate having a circuit pattern formed on a surface, in which the circuit pattern is connected electrically by a stud bump, includes (a) forming the circuit pattern and the stud bump by depositing a plating layer selectively on a seed layer of a carrier film, where the seed layer is laminated on a surface of the carrier film, (b) laminating and pressing the carrier film on an insulation layer such that the circuit pattern and the stud bump face the insulation layer, and (c) removing the carrier film and the seed layer, allows the circuit interconnection to be realized using a copper (Cu) stud bump, so that a drilling process for interconnection is unnecessary, the degree of freedom for circuit design is improved, a via land is made unnecessary and the size of a via is small, to allow higher density in a circuit.

Abstract translation: 公开了掩埋图案基板及其制造方法。 一种制造埋设图形衬底的方法，其中电路图案形成在电路图形通过柱形凸块电连接的表面上，包括：（a）通过在 晶种层层叠在载体膜的表面上的载体膜的种子层，（b）在绝缘层上层叠压制载体膜，使得电路图案和柱状凸块面向绝缘层，和 c）去除载体膜和种子层，允许使用铜（Cu）柱状凸块实现电路互连，使得不需要用于互连的钻孔工艺，提高了电路设计的自由度，通孔焊盘 不必要，并且通孔的尺寸小，以允许电路中的较高密度。

公开(公告)号：US20070059918A1

公开(公告)日：2007-03-15

申请号：US11520730

申请日：2006-09-14

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H01L21/4763

CPC classification number: H05K3/4691 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K1/189 ,  H05K3/4623 ,  H05K2201/056 ,  H05K2201/09536 ,  H05K2201/10515 ,  H05K2203/049 ,  H05K2203/063 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention relates to a rigid-flexible multi-layer printed circuit board comprising: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. According the present invention, when the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.

Abstract translation: 硬质柔性多层印刷电路板技术领域本发明涉及一种柔性多层印刷电路板，包括：柔性基板，其两侧形成有可弯曲的电路; 层叠在柔性基板上的刚性基板和电路形成在两侧，并且形成有安装半导体芯片的空腔; 以及粘合柔性基板和刚性基板并具有绝缘性的粘合片。 根据本发明，当安装相同数量的半导体芯片或实施POP时，封装的整体厚度可以较低。 此外，可以使用空间作为芯层的厚度来安装另外两个半导体芯片，并且可以实现当传统技术中安装在底部基板上的半导体芯片的数量变为二倍时的结构不可行。