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公开(公告)号：US20120279061A1
公开(公告)日：2012-11-08
申请号：US13549440
申请日：2012-07-14
Applicant: Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
Inventor： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC: H05K3/40
CPC classification number: H01L23/49827 , H01L23/498 , H01L23/49838 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H05K1/0222 , H05K1/115 , H05K3/4602 , H05K2201/096 , H05K2201/09609 , Y10T29/49155 , Y10T29/49165 , Y10T29/4919 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599 , H01L2224/05099
Abstract: A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.
Abstract translation: 在衬底/芯片组件中制造衬底通孔结构的方法包括以下步骤：在衬底/芯片组件中布置用于电互连的中心通孔叠层; 以及通过堆叠提供围绕中心的多个堆叠的通孔。 多个堆叠的通孔通过堆叠环绕中心，导致结构上没有隔离的通孔堆叠。 多个堆叠的通孔具有功能和非功能通孔。
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12.发明授权Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法公开(公告)号：US08258410B2
公开(公告)日：2012-09-04
申请号：US12020534
申请日：2008-01-26
Applicant: Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
Inventor： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
CPC classification number: H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.
Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 平板通孔着陆包括顺应中心区域; 以及用于连接板状通孔底板的柔性中心区域的弹簧状刚度减小连接器。
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Patent Agency Ranking
13.发明申请EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC SUBSTRATES 审中-公开用于电子基板中的可靠堆叠VIAS的嵌入式约束盘公开(公告)号：US20090189289A1
公开(公告)日：2009-07-30
申请号：US12020561
申请日：2008-01-27
Applicant: Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
Inventor： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC: H01L23/52 , H01L23/535
CPC classification number: H01L23/49827 , H01L23/49822 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/15311
Abstract: A substrate via structure for stacked vias includes: a plurality of stacked vias, wherein each via is disposed on a landing; and at least one constrainer disc surrounding at least one via, for constraining in-plane deformation of the substrate via structure. The constrainer disc is embedded such that the constrainer disc is disposed between two layers of resin. The constrainer discs may be made of copper. The constrainer disc may be circular or square-shaped. Preferably there is a dielectric gap between the constrainer disc and the via.
Abstract translation: 用于堆叠通孔的衬底通孔结构包括：多个堆叠的通孔，其中每个通孔设置在层站上; 以及围绕至少一个通孔的至少一个约束盘，用于限制基板经由结构的平面内变形。 约束盘被嵌入，使得约束盘设置在两层树脂之间。 约束盘可以由铜制成。 约束盘可以是圆形或正方形。 优选地，在约束盘和通孔之间存在电介质间隙。
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14.发明申请Variable interconnect geometry for electronic packages and fabrication methods 有权用于电子封装和制造方法的可变互连几何公开(公告)号：US20080245559A1
公开(公告)日：2008-10-09
申请号：US11805693
申请日：2007-05-24
Applicant: Suresh K. Sitaraman , Karan Kacker , Thomas Sokol
Inventor： Suresh K. Sitaraman , Karan Kacker , Thomas Sokol
CPC classification number: H01R13/2407 , H01L23/3114 , H01L24/11 , H01L24/13 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , Y10T29/49224 , H01L2924/00015 , H01L2924/00
Abstract: Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.
Abstract translation: 公开了形成在基板上的可变互连几何形状，其允许互连的增加的电性能而不损害机械可靠性。 互连的顺应性从基板的中心到基板的边缘不同。 顺应性的变化可以是逐步的还是连续的。 示例性的低顺应性互连包括柱状互连，并且示例性的高符合性互连包括螺旋互连。 可以使用通过顺序光刻和电镀工艺在晶片级上批量制造互连的成本有效的实现。
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15.发明申请CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD 有权电子基板可靠堆叠构造 - 纵向硬度控制方法公开(公告)号：US20120299195A1
公开(公告)日：2012-11-29
申请号：US13569826
申请日：2012-08-08
Applicant: Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
Inventor： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC: H01L23/48 , H01L21/768
CPC classification number: H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.
Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括厚度基本为3μm的板状通孔着落。 镀层通孔着色包括蚀刻图案和铜顶表面。
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16.发明申请CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD 有权电子基板可靠堆叠构造 - 纵向硬度控制方法公开(公告)号：US20120267158A1
公开(公告)日：2012-10-25
申请号：US13539480
申请日：2012-07-01
Applicant: Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
Inventor： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
CPC classification number: H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.
Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 镀层通孔着色包括蚀刻图案。
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17.发明申请Construction of Reliable Stacked Via in Electronic Substrates - Vertical Stiffness Control Method 有权电子基板中可靠堆叠通孔的构造 - 垂直刚度控制方法公开(公告)号：US20090188705A1
公开(公告)日：2009-07-30
申请号：US12020534
申请日：2008-01-26
Applicant: Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
Inventor： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC: H05K1/09
CPC classification number: H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.
Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 平板通孔着陆包括顺应中心区域; 以及用于连接板状通孔底板的柔性中心区域的弹簧状刚度减小连接器。
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