公开(公告)号：US08759151B2

公开(公告)日：2014-06-24

申请号：US13422429

申请日：2012-03-16

申请人： Thomas E. Lombardi ,  Donald Merte ,  Gregg B. Monjeau ,  David L. Questad ,  Son K. Tran

发明人： Thomas E. Lombardi ,  Donald Merte ,  Gregg B. Monjeau ,  David L. Questad ,  Son K. Tran

IPC分类号： H01L21/00

CPC分类号： H01L24/81 ,  B23K1/0016 ,  B23K3/087 ,  B23K2101/40 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/49894 ,  H01L24/01 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  Y10T29/41 ,  Y10T29/49117 ,  H01L2924/00

摘要： A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

摘要翻译： 提供了一种形成芯片组件的固定装置和方法。 夹具组件包括具有开口尺寸以容纳安装在层压板上的芯片的第一板。 固定装置还包括通过至少一个机械紧固机构配合到第一板的第二板。 夹具组件还包括由第一板和第二板的相对表面限定的并由第一板和第二板中的至少一个的凸起台阶部限定的空间。 这个空间与开幕式一致。 该空间的尺寸和形状使得层压体被限制在空间内并且直接邻接第一板和第二板的阶梯部分和相对表面以被限制在X，Y和Z方向上。

公开(公告)号：US20140033148A1

公开(公告)日：2014-01-30

申请号：US13557386

申请日：2012-07-25

申请人： Erwin B. Cohen ,  Mark C.H. Lamorey ,  Marek A. Orlowski ,  Douglas O. Powell ,  David L. Questad ,  David B. Stone ,  Paul R. Walling

发明人： Erwin B. Cohen ,  Mark C.H. Lamorey ,  Marek A. Orlowski ,  Douglas O. Powell ,  David L. Questad ,  David B. Stone ,  Paul R. Walling

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.

摘要翻译： 计算机实现的方法提供了倒装芯片封装的芯片载体的弹性模量图。 将包括芯片载体的每个层的每个垂直对准子区域的电介质和导电设计元件的设计数据建模为弹簧以提供弹性模量图。 确定芯片载体的子区域的弹性模量在芯片接合期间识别可能的机械故障位置并冷却倒装芯片封装。 将焊料凸块修改为芯片载体可以减少施加到识别的可能的机械故障位置的应力。 修改芯片载体设计以减少与识别出的可能的机械故障位置相关联的子区域的刚度，还可减少芯片连接和冷却的应力。

公开(公告)号：US08637392B2

公开(公告)日：2014-01-28

申请号：US12700863

申请日：2010-02-05

申请人： Charles L. Arvin ,  Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Brian R. Sundlof

发明人： Charles L. Arvin ,  Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Brian R. Sundlof

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/119 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01026 ,  H01L2924/01032 ,  H01L2924/00012 ,  H01L2924/00

摘要： A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

摘要翻译： 焊接互连结构设置有不可润湿的侧壁及其制造方法。 该方法包括在下面的表面上形成镍或镍合金支柱。 该方法还包括修改镍或镍合金柱的侧壁以防止在侧壁上的焊料润湿。

公开(公告)号：US20120139123A1

公开(公告)日：2012-06-07

申请号：US12960110

申请日：2010-12-03

申请人： Timothy H. Daubenspeck ,  Gary Lafontant ,  Ekta Misra ,  David L. Questad ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Thomas A. Wassick ,  Steven L. Wright

发明人： Timothy H. Daubenspeck ,  Gary Lafontant ,  Ekta Misra ,  David L. Questad ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Thomas A. Wassick ,  Steven L. Wright

IPC分类号： H01L23/52 ,  G06F17/50 ,  H01L21/44

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13006 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3511 ,  Y02P90/265 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/014

摘要： Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.

摘要翻译： 提供半导体结构，制造方法和设计结构。 该结构包括与芯片的下面的金属焊盘接触形成的至少一个偏移月牙形焊料通孔。 至少一个偏移月牙形通孔相对于下面的金属焊盘和下面的金属层中的至少一个与芯片的与下面的金属层电接触的互连直接电接触而偏移。

公开(公告)号：US07868459B2

公开(公告)日：2011-01-11

申请号：US11469950

申请日：2006-09-05

申请人： Jean Audet ,  Luc Guerin ,  David L. Questad ,  David J. Russell

发明人： Jean Audet ,  Luc Guerin ,  David L. Questad ,  David J. Russell

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor package is disclosed including a first capture pad isolated from an adjacent second capture pad by an insulator; a first plurality of electrically active vias connecting the first capture pad to the second capture pad; a third capture pad isolated from the second capture pad by an insulator; and a second plurality of electrically active vias connecting the second capture pad to the third capture pad. Each via of the first plurality of active vias is non-aligned with each via of the second plurality of active vias. The structure provides reduction of strain on the vias when a shear force is applied to a ball grid array used therewith while minimizing the degradation of the electrical signals.

摘要翻译： 公开了一种半导体封装，其包括通过绝缘体与相邻的第二捕获垫隔离的第一捕获垫; 将第一捕获垫连接到第二捕获垫的第一多个电活动通孔; 通过绝缘体与第二捕获垫隔离的第三捕获垫; 以及将第二捕获垫连接到第三捕获垫的第二多个电活动通孔。 第一多个有源通孔的每个通孔与第二多个有源通孔的每个通孔不对齐。 当将剪切力施加到与其一起使用的球栅阵列同时最小化电信号的劣化时，该结构提供通孔上的应变减小。

公开(公告)号：US07851911B2

公开(公告)日：2010-12-14

申请号：US12715523

申请日：2010-03-02

申请人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

发明人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L22/32 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2924/014 ,  H05K1/0268 ,  H05K3/3436 ,  H05K2203/163 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

摘要翻译： 用于形成该半导体芯片的半导体芯片。 半导体芯片包括M个常规焊料凸块结构和N个监测焊料凸块结构，M和N是正整数。 如果对半导体芯片执行倒装芯片处理，则N监视器焊料凸块结构对于冷却压力比对M规则焊料凸块结构更敏感。 冷却应力来自倒装芯片工艺的冷却步骤。 每个M规则焊料凸块结构电连接到电源或半导体芯片的器件。 N个监视器焊料凸块结构中的每一个都不电连接到电源或半导体芯片的器件。

公开(公告)号：US20090256257A1

公开(公告)日：2009-10-15

申请号：US12102035

申请日：2008-04-14

申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  David L. Questad ,  Wolfgang Sauter

发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  David L. Questad ,  Wolfgang Sauter

IPC分类号： H01L23/52 ,  H01L23/488 ,  H01L21/44

CPC分类号： H01L23/53295 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A structure and a method for forming the same. The structure includes a first dielectric layer, an electrically conductive bond pad on the first dielectric layer, and a second dielectric layer on top of the first dielectric layer and the electrically conductive bond pad. The electrically conductive bond pad is sandwiched between the first and second dielectric layers. The second dielectric layer includes N separate final via openings such that a top surface of the electrically conductive bond pad is exposed to a surrounding ambient through each final via opening of the N separate final via openings. N is a positive integer greater than 1.

摘要翻译： 一种结构及其形成方法。 该结构包括第一电介质层，第一电介质层上的导电接合焊盘，以及在第一电介质层和导电接合焊盘顶部的第二电介质层。 导电接合焊盘夹在第一和第二电介质层之间。 第二电介质层包括N个独立的最终通路孔，使得导电接合焊盘的顶表面暴露于通过N个单独的最终通孔的每个最终通孔的周围环境。 N是大于1的正整数。

公开(公告)号：US20080303021A1

公开(公告)日：2008-12-11

申请号：US12116655

申请日：2008-05-07

申请人： Jeffrey T. Coffin ,  Michael A. Gaynes ,  David L. Questad ,  Kamal K. Sikka ,  Hilton T. Toy ,  Jamil A. Wakil

发明人： Jeffrey T. Coffin ,  Michael A. Gaynes ,  David L. Questad ,  Kamal K. Sikka ,  Hilton T. Toy ,  Jamil A. Wakil

IPC分类号： G01R31/28

CPC分类号： H01L23/34 ,  H01L23/3735 ,  H01L23/42 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/3511 ,  Y10T29/49004 ,  Y10T29/49083 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/4935

摘要： Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.

摘要翻译： 披露的是导热板。 每个板被构造成使得当板结合到发热结构并经受使得发热结构的预定温度范围内的温度时，板和发热结构之间可以实现均匀的粘合剂填充的间隙 经。 另外，本公开提供了形成板并将板结合到发热结构的相关方法。 在一个实施例中，板是弯曲的并被建模以使发热结构的弯曲表面在预定温度范围内匹配。 在另一个实施例中，板是多层导电结构，其被配置为在与热产生结构相关的热负荷下经历相同的翘曲。 因此，当板与发热结构接合时，能够在任何温度下实现和保持均匀的粘合剂填充间隙。

公开(公告)号：US07312523B2

公开(公告)日：2007-12-25

申请号：US11161285

申请日：2005-07-28

申请人： Jean J. Audet ,  Jon A. Casey ,  Luc Guerin ,  David L. Questad ,  David J. Russell

发明人： Jean J. Audet ,  Jon A. Casey ,  Luc Guerin ,  David L. Questad ,  David J. Russell

IPC分类号： H01L23/053 ,  H01L23/12 ,  H01L23/48

CPC分类号： H05K1/116 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H01L2924/00

摘要： A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer; and a plurality of via lands extending radially outward from the via stack, wherein each of the plurality of via lands is diametrically larger than the RFP cap. Preferably, the RFP cap comprises a diameter of at least 300 μm. Preferably, each of the via lands comprises a substantially circular shape having a diameter of at least 400 μm. Moreover, the circuit board further comprises a ball grid array pad connected to the via stack; and input/output ball grid array pads connected to the ball grid array pad. Additionally, the circuit board further comprises metal planes in the dielectric layer.

摘要翻译： 电路板包括填充树脂的电镀（RFP）通孔; 在RFP通孔上的电介质层; 电介质层中的大致圆形的RFP帽，并连接到RFP通孔的上部开口; 电介质层中的通孔叠层; 以及从所述通孔叠层径向向外延伸的多个通孔焊盘，其中所述多个通路焊盘中的每一个在径向上大于所述RFP盖。 优选地，RFP帽包括至少300μm的直径。 优选地，每个通孔焊盘包括具有至少400μm直径的基本圆形形状。 此外，电路板还包括连接到通孔叠层的球栅阵列垫; 以及连接到球栅阵列垫的输入/输出球栅阵列垫。 此外，电路板还包括电介质层中的金属平面。

公开(公告)号：US07256503B2

公开(公告)日：2007-08-14

申请号：US11276380

申请日：2006-02-27

申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  David L. Questad

发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  David L. Questad

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81194 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83194 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/3512

摘要： A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.

摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括（a）基板和（b）包括N个芯片焊球，N是正整数的芯片，并且N个芯片焊球与基板电接触。 半导体结构还包括（c）分别在芯片的第一，第二，第三和第四角部处并夹在芯片和基板之间的第一，第二，第三和第四角底部填充区域。 半导体结构还包括（d）夹在芯片和衬底之间的主要底部填充区域。 第一，第二，第三和第四角底部填充区域，并且主底部填充区域基本上占据芯片和基板之间的整个空间。 第一，第二，第三和第四角底部填充区域的角底层填充材料与主要底部填充区域的主要底部填充材料不同。