公开(公告)号：US20120299195A1

公开(公告)日：2012-11-29

申请号：US13569826

申请日：2012-08-08

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括厚度基本为3μm的板状通孔着落。 镀层通孔着色包括蚀刻图案和铜顶表面。

公开(公告)号：US20120267158A1

公开(公告)日：2012-10-25

申请号：US13539480

申请日：2012-07-01

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 镀层通孔着色包括蚀刻图案。

公开(公告)号：US20090265028A1

公开(公告)日：2009-10-22

申请号：US12107064

申请日：2008-04-21

Applicant: Sri M. Sri-Jayantha ,  Arun Sharma ,  Vijayeshwar D. Khanna ,  Hien P. Dang ,  David J. Russell ,  Douglas O. Powell

Inventor： Sri M. Sri-Jayantha ,  Arun Sharma ,  Vijayeshwar D. Khanna ,  Hien P. Dang ,  David J. Russell ,  Douglas O. Powell

IPC: G06F19/00

CPC classification number: H05K3/0005 ,  H05K1/0271 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/0191 ,  H05K2201/09136

Abstract: A process for large scale production of a laminated organic substrate having reduced thermal warp.

Abstract translation: 用于大规模生产具有降低的热翘曲的层压有机基材的方法。

公开(公告)号：US20090188705A1

公开(公告)日：2009-07-30

申请号：US12020534

申请日：2008-01-26

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K1/09

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 平板通孔着陆包括顺应中心区域; 以及用于连接板状通孔底板的柔性中心区域的弹簧状刚度减小连接器。

公开(公告)号：US06830875B2

公开(公告)日：2004-12-14

申请号：US10266020

申请日：2002-10-07

Applicant: Stephen J. Fuerniss ,  Gary Johansson ,  Ross W. Keesler ,  John M. Lauffer ,  Voya R. Markovich ,  Peter A. Moschak ,  David J. Russell ,  William E. Wilson

Inventor： Stephen J. Fuerniss ,  Gary Johansson ,  Ross W. Keesler ,  John M. Lauffer ,  Voya R. Markovich ,  Peter A. Moschak ,  David J. Russell ,  William E. Wilson

IPC: G03F700

CPC classification number: H05K3/0023 ,  H05K1/056 ,  H05K3/445 ,  H05K3/4641 ,  H05K2203/1476 ,  Y10T29/49165

Abstract: A method for forming an electronic structure. Provides is a layer that includes a cylindrical volume of a photoimageable dielectric (PID) material, an annular volume of the PID material circumscribing the cylindrical volume, and a remaining volume of the PID material circumscribing the annular volume. The layer is photolithograhically exposed to radiation. The annular volume is fully cured by the radiation. The remaining volume is partially cured by the remaining volume by said radiation. The method prevents curing of the cylindrical volume, wherein the PID material in the cylindrical volume remains uncured.

Abstract translation: 一种形成电子结构的方法。 提供是包括可光成像电介质（PID）材料的圆柱体积，围绕圆柱体积的PID材料的环形体积以及围绕环形体积的PID材料的剩余体积的层。 该层被光刻地暴露于辐射。 环形体积被辐射完全固化。 剩余体积由所述辐射的剩余体积部分固化。 该方法防止圆柱体积的固化，其中圆柱体积中的PID材料保持未固化。

公开(公告)号：US06528218B1

公开(公告)日：2003-03-04

申请号：US09808334

申请日：2001-03-14

Applicant: Elizabeth Foster ,  Gary A. Johansson ,  Heike Marcello ,  David J. Russell

Inventor： Elizabeth Foster ,  Gary A. Johansson ,  Heike Marcello ,  David J. Russell

IPC: G03F711

CPC classification number: G03F7/0385 ,  G03F7/038 ,  H05K3/0023 ,  H05K3/4644 ,  H05K3/4676 ,  Y10T428/24851

Abstract: A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier; from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C.) comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0 to about 5% solvent; applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.

Abstract translation: 一种制造电路化基板的方法，其减少短路，并且不需要烘烤和得到的膜。 该方法使用溶剂含量小于约5％的光致成像电介质膜，当固化时玻璃化转变温度大于约110℃。提供具有约95％至约100的光致成像电介质膜 ％固体，并且包含：0％至约30％的固体，颗粒状流变改性剂; 约70％至约100％的环氧树脂体系的固体（20℃的液体），包含：约85％至约99.9％的环氧树脂; 和约0.1至15份的总树脂重量，阳离子光引发剂; 0至约5％的溶剂; 将光致成像电介质膜施加到电路化基板上; 并将膜暴露于光化辐射。

公开(公告)号：US06195264B1

公开(公告)日：2001-02-27

申请号：US09195389

申请日：1998-11-18

Applicant: John M. Lauffer ,  Heike Marcello ,  David J. Russell

Inventor： John M. Lauffer ,  Heike Marcello ,  David J. Russell

IPC: H05K118

CPC classification number: H05K3/0061 ,  H01L21/4803 ,  H01L23/36 ,  H01L2924/0002 ,  H05K1/183 ,  H05K3/0023 ,  H05K3/386 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/53178 ,  Y10T156/1798 ,  H01L2924/00

Abstract: A cavity-type chip module. The module is formed with an adhesive joining layer of photoimageable material interposed between a metal stiffener and a laminate top layer with a central aperture defined in the top layer. The photoimageable material is exposed to actinic radiation, except for an area corresponding to the aperture in the top layer. The unexposed area of photoimageable material is developed away to form a window in the joining layer. The top layer, joining layer, and stiffener are laminated together with the window and aperture aligned, and with a portion of the stiffener spanning the aperture to define a cavity in the resulting substrate. The removal of the unexposed photoimageable material, and the selective exposure of the joining layer to actinic radiation, keep the cavity free of photoimageable material and inhibit bleeding of the photoimageable material into the cavity from its inner edge. As a result, a semiconductor component can be flush mounted in the cavity with optimal thermal conductivity to the metal stiffener.

Abstract translation: 腔型芯片模块。 该模块形成有介于金属加强件和层压顶层之间的可光成像材料的粘合剂接合层，中间孔限定在顶层中。 光致成像材料暴露于光化辐射，除了对应于顶层中的孔的区域外。 可光成像材料的未曝光区域被开发出来以在接合层中形成窗口。 将顶层，接合层和加强件层压在一起，窗口和孔对齐，并且加强件的一部分跨越孔以在所得到的基底中限定空腔。 未曝光的可光成像材料的去除以及将接合层选择性地暴露于光化辐射，保持空腔不含可光成像的材料并且抑制可光成像材料从其内边缘渗入空腔。 结果，半导体部件可以齐平地安装在空腔中，对金属加强件具有最佳的导热性。

公开(公告)号：US6080668A

公开(公告)日：2000-06-27

申请号：US58266

申请日：1998-04-10

Applicant: John M. Lauffer ,  David J. Russell

Inventor： John M. Lauffer ,  David J. Russell

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/00 ,  H05K3/28 ,  H05K3/40 ,  H05K3/46 ,  H01L21/44

CPC classification number: H05K3/0023 ,  H01L21/4857 ,  H01L23/49894 ,  H05K3/4614 ,  H01L2924/0002 ,  H05K2201/0355 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K3/0094 ,  H05K3/28 ,  H05K3/4069 ,  H05K3/4652

Abstract: A method for manufacturing electronic circuit assemblies. A layer of dielectric material is attached to a layer of electrically conductive material. Vias are formed in the layer of dielectric material and filled with conductive paste material. The resulting assembly is attached to a substrate. Because the vias are formed and filled before the dielectric layer is attached to the substrate, it is not necessary to scrap the entire multi-layer structure, which includes the substrate and all the attached layers, when a problem occurs during via formation or filling. This increases the overall yield for the entire circuit assembly manufacturing process.

Abstract translation: 一种用于制造电子电路组件的方法。 电介质材料层附着在导电材料层上。 通孔形成在电介质材料层中并填充有导电糊材料。 所得到的组件附接到基底。 由于在介电层附着到基板之前形成和填充通孔，所以当通孔形成或填充期间出现问题时，不需要废除包括基板和所有附着层在内的整个多层结构。 这增加了整个电路组件制造过程的总产量。

公开(公告)号：US5953623A

公开(公告)日：1999-09-14

申请号：US835690

申请日：1997-04-10

Applicant: Christina M. Boyko ,  Anthony P. Ingraham ,  Voya R. Markovich ,  David J. Russell

Inventor： Christina M. Boyko ,  Anthony P. Ingraham ,  Voya R. Markovich ,  David J. Russell

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/44

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H05K3/3436 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2203/0435 ,  H05K2203/073 ,  H05K3/3463 ,  Y02P70/613

Abstract: A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.

Abstract translation: 焊料互连优选地使用富铅球，以将低温芯片附接到任何更高级别的封装衬底上。 在使用标准工艺形成焊球之后，使用光致抗蚀剂形成球限制金属掩模。 使用锡水溶液浸渍法将优选纯锡的薄盖层沉积在焊球的表面上。

公开(公告)号：US5304457A

公开(公告)日：1994-04-19

申请号：US956836

申请日：1992-10-05

Applicant: Richard A. Day ,  Jeffrey D. Gelorme ,  David J. Russell ,  Stephen J. Witt

Inventor： Richard A. Day ,  Jeffrey D. Gelorme ,  David J. Russell ,  Stephen J. Witt

IPC: G03C1/725

CPC classification number: G03C1/725

Abstract: An improved photoimagable cationically polymerizable epoxy based coating material is provided. The material includes an epoxy resin system consisting essentially of between about 10% and about 80% by weight of a polyol resin which is a condensation product of epichlorohydrin and bisphenol A having a molecular weight of between about 40,000 and 130,000; between about 20% and about 90% by weight of an epoxidized octafunctional bisphenol A formaldehyde novolak resin having a molecular weight of 4,000 to 10,000; and if flame retardancy is required between about 35% and 50% by weight of an epoxidized glycidyl ether of tetrabromo bisphenol A having a softening point of between about 60.degree. C. and about 110.degree. C. and a molecular weight of between about 600 and 2,500. To this resin system is added about 0.1 to about 15 parts by weight per 100 parts of resin of a cationic photoinitiator capable of initiating polymerization of said epoxidized resin system upon exposure to actinic radiation; the system being further characterized by having an absorbance of light in the 330 to 700 nm region of less than 0.1 for a 2.0 mil thick film. Optionally a photosensitizer such as perylene and its derivatives or anthracene and its derivatives may be added.