公开(公告)号：US20100148825A1

公开(公告)日：2010-06-17

申请号：US12591701

申请日：2009-11-30

Applicant: Jae-chul Park ,  I-hun Song ,  Young-soo Park ,  Kee-won Kwon ,  Chang-jung Kim ,  Kyoung-kook Kim ,  Sung-ho Park ,  Sung-hoon Lee ,  Sang-wook Kim ,  Sun-il Kim

Inventor： Jae-chul Park ,  I-hun Song ,  Young-soo Park ,  Kee-won Kwon ,  Chang-jung Kim ,  Kyoung-kook Kim ,  Sung-ho Park ,  Sung-hoon Lee ,  Sang-wook Kim ,  Sun-il Kim

IPC: H03K19/094 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/336 ,  H01L27/088

CPC classification number: H01L29/7869 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11807 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/41733 ,  H01L29/78648

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件可以是包括p型氧化物TFT和n型氧化物TFT的互补器件。 半导体器件可以是诸如逆变器，NAND器件或NOR器件的逻辑器件。

公开(公告)号：US07618186B2

公开(公告)日：2009-11-17

申请号：US11790174

申请日：2007-04-24

Applicant: Duk-Min Kwon ,  Kee-Won Kwon

Inventor： Duk-Min Kwon ,  Kee-Won Kwon

IPC: G01K7/00

CPC classification number: G01K7/015 ,  G01K15/00 ,  G01K2219/00

Abstract: A self-calibrating temperature sensor and a method thereof are provided. The self-calibrating temperature sensor may include a reference voltage generator to generate a reference voltage based on temperature, a digital-to-analog converter to convert a first digital signal into an analog sensing voltage, a comparator to compare the reference voltage with the analog sensing voltage, and to generate a comparison result signal, a digital signal generator to generate and update the first digital signal based on the comparison result signal, a first storage circuit to store the first digital signal based on a first temperature, a data output unit to output data corresponding to a second temperature based on the first digital signal and a second digital signal output from the first storage circuit.

Abstract translation: 提供了一种自校准温度传感器及其方法。 自校准温度传感器可以包括参考电压发生器以产生基于温度的参考电压，数模转换器将第一数字信号转换为模拟感测电压，比较器将参考电压与模拟 并且产生比较结果信号，数字信号发生器，用于基于比较结果信号产生和更新第一数字信号;第一存储电路，用于基于第一温度存储第一数字信号;数据输出单元 基于第一数字信号输出对应于第二温度的数据和从第一存储电路输出的第二数字信号。

公开(公告)号：US07457181B2

公开(公告)日：2008-11-25

申请号：US11600552

申请日：2006-11-16

Applicant: Hoon Lee ,  Kee-Won Kwon

Inventor： Hoon Lee ,  Kee-Won Kwon

IPC: G11C7/02

CPC classification number: G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065

Abstract: A memory device has a global input/output line pair configured for data transfer. The memory device includes a sense amplifier, a detecting unit and a detect control signal generating unit. The sense amplifier is coupled to the global input/output line pair. The detecting unit detects a potential difference between the global input/output line pair. The detect control signal generating unit disables an operation of the sense amplifier and precharges the global input/output line pair to a predetermined voltage. A precharge operation of a memory device may be performed at a higher speed so that a high speed operation of the memory device may be achieved. In addition, the operating time of the sense amplifier may be decreased so that the power consumption of the memory device may be reduced.

Abstract translation: 存储器件具有配置用于数据传输的全局输入/输出线对。 存储装置包括读出放大器，检测单元和检测控制信号生成单元。 读出放大器耦合到全局输入/输出线对。 检测单元检测全局输入/输出线对之间的电位差。 检测控制信号产生单元禁止读出放大器的操作，并将全局输入/输出线对预充电到预定电压。 可以以更高的速度执行存储器件的预充电操作，从而可以实现存储器件的高速操作。 此外，可以减小读出放大器的工作时间，从而可以降低存储器件的功耗。

公开(公告)号：US20070133315A1

公开(公告)日：2007-06-14

申请号：US11604708

申请日：2006-11-28

Applicant: Uk-song Kang ,  Kee-won Kwon

Inventor： Uk-song Kang ,  Kee-won Kwon

IPC: G11C7/10

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/408 ,  G11C2207/104 ,  G11C2211/4061

Abstract: A dynamic random access memory device having reduced power consumption and a refresh cycle method. The memory device includes a monitoring address storage unit storing multiple monitoring addresses, an error correction code (ECC) engine detecting whether or not an error occurs in monitoring bits corresponding to the monitoring addresses, and a refresh cycle determining circuit adjusting a self refresh cycle depending on whether or not an error occurs in the monitoring bits.

Abstract translation: 具有降低功耗的动态随机存取存储器件和刷新循环方法。 存储装置包括存储多个监视地址的监视地址存储单元，检测在与监视地址相对应的监视位中是否发生错误的纠错码（ECC）引擎，以及刷新周期确定电路，其根据 关于监视位中是否发生错误。

公开(公告)号：US07199632B2

公开(公告)日：2007-04-03

申请号：US11147629

申请日：2005-06-08

Applicant: Byung-Kwan Chun ,  Kee-Won Kwon

Inventor： Byung-Kwan Chun ,  Kee-Won Kwon

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: A duty cycle correction circuit for use in a semiconductor device, which synchronizes with an external clock and corrects a duty cycle, is provided. The duty cycle correction circuit includes a modulator of an inverter structure having at least one or more transistors. The modulator receives a control signal through a source terminal and a bulk of any one of the transistors and corrects a duty cycle in response to an external clock signal. The duty cycle correction circuit also includes a driver that converts an output signal of the modulator into a full swing level and outputs the converted output signal of the modulator, and a feedback loop that generates the control signal in response to an output signal of the driver.

Abstract translation: 提供了一种用于与外部时钟同步并且校正占空比的半导体器件中的占空比校正电路。 占空比校正电路包括具有至少一个或多个晶体管的反相器结构的调制器。 调制器通过源极端子和任何一个晶体管的大部分接收控制信号，并根据外部时钟信号校正占空比。 占空比校正电路还包括将调制器的输出信号转换成全摆幅电平并输出调制器的转换的输出信号的驱动器，以及响应于驱动器的输出信号产生控制信号的反馈回路 。

公开(公告)号：US07145493B2

公开(公告)日：2006-12-05

申请号：US11141536

申请日：2005-05-31

Applicant: Kee-Won Kwon

Inventor： Kee-Won Kwon

IPC: H03M1/66

CPC classification number: H03M1/1061 ,  H03M1/785

Abstract: A DAC circuit can include a plurality of current source circuits configured to operate responsive to respective different bias voltage signals and respective true and complementary binary digit signals.

Abstract translation: DAC电路可以包括多个电流源电路，其被配置为响应于各个不同的偏置电压信号和相应的真和互补的二进制数字信号进行操作。

公开(公告)号：US5796133A

公开(公告)日：1998-08-18

申请号：US782827

申请日：1997-01-13

Applicant: Kee-Won Kwon ,  Chang-Seok Kang

Inventor： Kee-Won Kwon ,  Chang-Seok Kang

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11502 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/60

Abstract: In a semiconductor device having a ferroelectric capacitor and manufacturing method thereof, a spacer comprising a low dielectric material is formed on the side surfaces of a plurality of lower electrodes separated into each cell unit, and a ferroelectric film is formed on the lower electrodes whereon the low dielectric material spacer is formed, and an upper electrode is formed on the ferroelectric film, to thereby prevent an error which may be caused between the adjacent lower electrodes.

Abstract translation: 在具有铁电电容器的半导体器件及其制造方法中，在分离成各单元的多个下电极的侧面形成有包含低电介质材料的间隔物，在下电极上形成强电介质膜， 形成低电介质材料隔离物，并且在铁电体膜上形成上电极，从而防止在相邻的下电极之间可能引起的误差。

公开(公告)号：US5552337A

公开(公告)日：1996-09-03

申请号：US301437

申请日：1994-09-09

Applicant: Kee-won Kwon ,  Chang-seok Kang

Inventor： Kee-won Kwon ,  Chang-seok Kang

IPC: H01L21/205 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L28/40

Abstract: A capacitor for a semiconductor memory device employs a tantalum pentoxide film as a dielectric film. The dielectric film is made from tantalum pentoxide film doped with silicon over a first electrode. A second electrode is then formed over the dielectric film. Accordingly, in the method for manufacturing the device, although the dielectric constant of the dielectric film is somewhat lower than the conventional pure tantalum pentoxide film due to the silicon doped within the tantalum pentoxide film, leakage current is reduced and breakdown voltage is increased. Therefore, the dielectric film according to the present invention exhibits excellent electrical characteristics and high reliability.

Abstract translation: 用于半导体存储器件的电容器使用五氧化二钽膜作为电介质膜。 电介质膜由在第一电极上掺杂有硅的五氧化二钽膜制成。 然后在电介质膜上形成第二电极。 因此，在该器件的制造方法中，由于在五氧化二钽膜内掺杂了硅，电介质膜的介电常数比现有的五氧化二钽膜略低，所以漏电流降低，击穿电压增加。 因此，根据本发明的电介质膜显示出优异的电特性和高可靠性。

公开(公告)号：US09330743B2

公开(公告)日：2016-05-03

申请号：US14677991

申请日：2015-04-03

Applicant: Chan-Kyung Kim ,  Kee-Won Kwon ,  Su-A Kim ,  Chul-Woo Park ,  Jae-Youn Youn

Inventor： Chan-Kyung Kim ,  Kee-Won Kwon ,  Su-A Kim ,  Chul-Woo Park ,  Jae-Youn Youn

IPC: G11C11/00 ,  G11C11/16 ,  G11C5/08 ,  G11C7/06 ,  G11C5/02 ,  G11C13/00 ,  G11C11/4091

CPC classification number: G11C11/16 ,  G11C5/025 ,  G11C5/08 ,  G11C7/065 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/4091 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

Abstract translation: 电阻型存储器件的存储核心至少包括耦合到位线的第一电阻型存储单元，第一电阻转换器和位线读出放大器。 第一电阻转换器在第一节点处耦合到位线。 第一电阻转换器基于读列选择信号将第一电阻型存储单元的电阻转换成相应的电压。 位线读出放大器耦合到第一节点处的位线，并且耦合到第二节点处的互补位线。 位线检测放大器响应于感测控制信号而感测和放大位线和互补位线的电压差。

公开(公告)号：US20150364187A1

公开(公告)日：2015-12-17

申请号：US14660530

申请日：2015-03-17

Applicant: Chan-Kyung KIM ,  Kee-Won KWON

Inventor： Chan-Kyung KIM ,  Kee-Won KWON

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C2013/0054

Abstract: A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

Abstract translation: 电阻式存储器件可以包括电阻单元阵列和片上电阻测量电路。 电阻单元阵列可以包括多个电阻存储单元。 片上电阻测量电路可以被配置为基于与电阻性存储器单元的第一存储单元的单元电阻对应的单元电流来产生大于或小于第一电流的第一电流和第二电流，并且生成 分别基于第一和第二电流的第一和第二数字信号。