公开(公告)号：US06930948B2

公开(公告)日：2005-08-16

申请号：US10621165

申请日：2003-07-15

申请人： Kyu-Chan Lee ,  Sang-Jae Rhee ,  Jung-Yong Choi ,  Jong-Hyun Choi ,  Jong-Sik Na ,  Jae-Hoon Kim

发明人： Kyu-Chan Lee ,  Sang-Jae Rhee ,  Jung-Yong Choi ,  Jong-Hyun Choi ,  Jong-Sik Na ,  Jae-Hoon Kim

IPC分类号： G11C5/14 ,  G11C11/00

CPC分类号： G11C5/147

摘要： An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

摘要翻译： 外部高/低电压兼容半导体存储器件包括内部电压焊盘，内部电压产生电路和内部电压控制信号产生电路。 内部电压焊盘将低外部电压与内部电压连接，并且内部电压产生电路响应于内部电压控制信号和高外部电压而产生内部电压。 内部电压控制信号发生电路根据高或低的外部电压产生内部电压控制信号。 因此，由于内部电压控制信号，可以管理半导体存储器件的数据库，而不将数据库分类为用于低电压的高电压数据库和数据库。 此外，内部电压电平稳定，因为根据外部电压的电压电平调节提供给内部电压的电荷。

公开(公告)号：US06909654B2

公开(公告)日：2005-06-21

申请号：US10633562

申请日：2003-08-05

申请人： Jae-Hoon Joo ,  Jin-Seok Lee ,  Sang-Seok Kang ,  Kyu-Chan Lee ,  Byung-Heon Kwak ,  Byung-Chul Kim

发明人： Jae-Hoon Joo ,  Jin-Seok Lee ,  Sang-Seok Kang ,  Kyu-Chan Lee ,  Byung-Heon Kwak ,  Byung-Chul Kim

IPC分类号： H01L27/108 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  H01L21/8242 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C2207/2227

摘要： A bit line pre-charge circuit of a semiconductor memory device includes a pre-charge circuit connected between a pair of bit lines for pre-charging the pair of bit lines in response to a pre-charge control signal and a pre-charge voltage transmitting circuit for transmitting a pre-charge voltage to the pre-charge circuit in response to the pre-charge control signal. A voltage drop in a pre-charge voltage generation line may be prevented when a short circuit is formed between a word line and a pair of bit lines, and current consumption during a standby operation of the semiconductor memory device may also be reduced, by preventing current from flowing from the pair of bit lines to the pre-charge voltage generation line.

摘要翻译： 半导体存储器件的位线预充电电路包括连接在一对位线之间的预充电电路，用于响应于预充电控制信号和预充电电压发射来对该对位线进行预充电 电路，用于响应于预充电控制信号将预充电电压发送到预充电电路。 当在字线和一对位线之间形成短路时，可以防止预充电电压产生线中的电压降，并且还可以通过防止在半导体存储器件的待机操作期间的电流消耗 电流从一对位线流向预充电电压产生线。

公开(公告)号：US20050116693A1

公开(公告)日：2005-06-02

申请号：US11001802

申请日：2004-12-01

申请人： Sang-Hyun Jang ,  Kyu-Chan Lee ,  Jong-Dae Kim ,  Jae-Hun Jeong

发明人： Sang-Hyun Jang ,  Kyu-Chan Lee ,  Jong-Dae Kim ,  Jae-Hun Jeong

IPC分类号： H02M3/155 ,  G05F1/10 ,  H02H7/12 ,  H02M3/00 ,  H02M3/156

CPC分类号： H02M1/36 ,  Y10S323/908

摘要： An inrush current prevention circuit for a DC-DC converter is provided and in preferred aspects comprises a switching element that transforms an input voltage by being switched on and off and outputs the transformed voltage. A filter filtrates the outputted voltage, transformed via the switching element, and outputs the filtrated voltage as an output voltage. A reference voltage generator generates a reference voltage. An error amplifier compares the reference voltage and output voltage and outputs an error signal. A Pulse Width Modulation (PWM) signal generator generates a PWM signal to switch on and off the switching element according to the error signal. An on-off circuit either transmits or isolates the PWM signal to the switching element. An Electronic Control Unit (ECU) controls the on-off circuit. Preferred systems of the invention can prevent an inrush current immediately following power input or during reactivation of the DC-DC converter.

摘要翻译： 提供了一种用于DC-DC转换器的浪涌电流防止电路，并且在优选的方面包括通过接通和断开来转换输入电压并输出变换的电压的开关元件。 滤波器对通过开关元件进行变换的输出电压进行滤波，并输出滤波电压作为输出电压。 参考电压发生器产生参考电压。 误差放大器比较参考电压和输出电压，并输出误差信号。 脉冲宽度调制（PWM）信号发生器根据误差信号产生PWM信号以接通和断开开关元件。 开关电路将PWM信号传输或隔离到开关元件。 电子控制单元（ECU）控制开关电路。 本发明的优选系统可以防止在电力输入之后或在重新激活DC-DC转换器期间的浪涌电流。

公开(公告)号：US06233196B1

公开(公告)日：2001-05-15

申请号：US09351718

申请日：1999-07-12

申请人： Kyu-chan Lee

发明人： Kyu-chan Lee

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C5/025 ,  G11C8/10

摘要： Multi-bank integrated circuit memory devices include a plurality of banks of memory cells that are divided into pairs of sub-banks of memory cells. The sub-banks of memory cells are arranged in a plurality of rows and columns of sub-banks of memory cells. The pairs of sub-banks extend diagonally relative to the plurality of rows and columns of sub-banks of memory cells. The pairs of sub-banks of the respective banks preferably are adjacent one another and extend diagonally relative to the plurality of rows and columns of sub-banks of memory cells. By providing diagonally extending sub-banks, the row address lines that extend between respective sub-banks of each bank may occupy reduced area. More specifically, row address lines that extend between pairs of sub-banks in same adjacent rows and same adjacent columns can cross over one another to thereby allow reduced area.

摘要翻译： 多组集成电路存储器件包括被划分成存储单元的子组对的多个存储单元组。 存储单元的子库被布置在多个存储单元子行的行和列中。 这些子库对相对于存储单元的子行的多个行和列倾斜地延伸。 各个分组的子组对优选地彼此相邻并且相对于存储单元的子行的多个行和列倾斜延伸。 通过提供对角延伸的子库，在每个存储体的相应子存储体之间延伸的行地址行可以占用减少的区域。 更具体地说，在相同的相邻行和相邻的相邻列之间延伸的子行对之间的行地址行可以彼此交叉，从而允许减少的区域。

公开(公告)号：US6005825A

公开(公告)日：1999-12-21

申请号：US178734

申请日：1998-10-27

申请人： Kyu-chan Lee ,  Nam-jong Kim

发明人： Kyu-chan Lee ,  Nam-jong Kim

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/22

摘要： A synchronous semiconductor memory device having a wave pipelining control structure and a method of outputting data therefrom. A register for storing the data output from a memory cell is controlled by a control signal in response to first and second external clock signals. The level transition of the control signal derived from the first clock is delayed, so that data output malfunctioning is prevented even though manufacturing process conditions are changed.

摘要翻译： 一种具有波形流水线控制结构的同步半导体存储器件以及从其输出数据的方法。 用于存储从存储器单元输出的数据的寄存器由响应于第一和第二外部时钟信号的控制信号控制。 从第一时钟导出的控制信号的电平转换被延迟，从而即使改变制造工艺条件，也防止数据输出故障。

公开(公告)号：US5770957A

公开(公告)日：1998-06-23

申请号：US825227

申请日：1997-03-19

申请人： Kyu-chan Lee

发明人： Kyu-chan Lee

IPC分类号： G06F1/32 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  H03B1/00

CPC分类号： G11C7/06

摘要： A signal generator produces enable signals for bitline sense amplifiers in a semiconductor device. The signal generator includes a first driving element for producing a first enable signal at a first output line in response to first and second control signals, a second driving element for producing a second enable signal at a second output line in response to inverted signals of the first and second control signals, and an equalizing element connected between the first output line and the second output line for equalizing the first and second output lines in response to a third control signal. A control signal generating element generates the first, second, and third control signals, and inverted signals thereof, in response to predetermined input signals. The DC current generated from an output driver and the charging and discharging current of output loading can be reduced, to thereby reduce power consumption. Also, when the output signals are applied as enable signals of bitline sense amplifiers, an initial invalid sensing the bitline sense amplifier circuits can be avoided.

摘要翻译： 信号发生器在半导体器件中产生用于位线读出放大器的使能信号。 信号发生器包括：第一驱动元件，用于响应于第一和第二控制信号在第一输出线处产生第一使能信号;第二驱动元件，用于响应于第二输出线的反相信号在第二输出线处产生第二使能信号 第一和第二控制信号，以及连接在第一输出线和第二输出线之间的均衡元件，用于响应于第三控制信号对第一和第二输出线进行均衡。 控制信号产生元件响应于预定的输入信号产生第一，第二和第三控制信号及其反相信号。 可以减少从输出驱动器产生的直流电流和输出负载的充放电电流，从而降低功耗。 此外，当输出信号被施加作为位线读出放大器的使能信号时，可以避免初始无效感测位线读出放大器电路。

公开(公告)号：US5761135A

公开(公告)日：1998-06-02

申请号：US706223

申请日：1996-09-03

申请人： Kyu-chan Lee

发明人： Kyu-chan Lee

IPC分类号： G11C11/401 ,  G11C8/08 ,  G11C8/14 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C8/14

摘要： An integrated circuit memory device includes an array of memory cells arranged into rows and columns. A main word line decoder receives a first portion of a row address and generates a main word line activation signal on a predetermined word line in response thereto. A word driver predecoder receives a second portion of the row address and generates a sub-row activation signal in response thereto. A sub-word line driver generates a sub-word line activation signal on an output node. This sub-word line driver includes a pull-down transistor, a pull-up transistor, and a driving transistor. The pull-down transistor electrically connects the output node to a ground terminal in response to an inverse of the sub-row activation signal. The pull-up transistor transfers the sub-row activation signal to the output node in response to the main word line activation signal. The driving transistor transfers the main word line activation signal to the output node in response to the sub-row activation signal. A sub-word line electrically connects the output node and a predetermined memory cell so that the predetermined memory cell is activated in response to the sub-word line activation signal.

摘要翻译： 集成电路存储器件包括排列成行和列的存储单元阵列。 主字线解码器接收行地址的第一部分，并响应于此在一预定字线上产生主字线激活信号。 字驱动器预解码器接收行地址的第二部分并响应于此生成子行激活信号。 子字线驱动器在输出节点上产生子字线激活信号。 该子字线驱动器包括下拉晶体管，上拉晶体管和驱动晶体管。 下拉晶体管响应于子行激活信号的倒数将输出节点电连接到接地端子。 上拉晶体管响应于主字线激活信号将子行激活信号传送到输出节点。 驱动晶体管响应于子行激活信号将主字线激活信号传送到输出节点。 子字线路电连接输出节点和预定的存储器单元，使得响应于子字线激活信号激活预定存储器单元。

公开(公告)号：US5757716A

公开(公告)日：1998-05-26

申请号：US766370

申请日：1996-12-12

申请人： Kyu-Chan Lee

发明人： Kyu-Chan Lee

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

CPC分类号： G11C29/81 ,  G11C29/832

摘要： Programmable disabling and selection circuits operate on a block level for integrated circuit memory devices. Thus, a redundant block can be substituted for a block having more defective rows and/or columns than the number of redundant rows and/or columns which are provided in the integrated circuit memory devices. A plurality of normal block selection circuits are included, a respective one of which produces a respective normal block selection signal in response to an address of a respective one of the plurality of blocks of memory cells. A plurality of programmable block selection circuits are also included, a respective one of which is connected between the respective one of the plurality of normal block selection circuits and a respective one of the plurality of blocks of memory cells. Each programmable block selection circuit includes a first fuse, the activation of which blocks the corresponding one of the plurality of normal block selection circuits. Each of the programmable block selection circuits further includes a plurality of second fuses, the activation of which generates a replacement address for the corresponding one of the plurality of blocks of memory cells. A plurality of block disable circuits are also included, a respective one of which is connected to a respective one of the plurality of blocks of memory cells. Each of the plurality of block disable circuits includes a fuse, the activation of which disables the corresponding one of the plurality of blocks of memory cells.

摘要翻译： 可编程禁用和选择电路在集成电路存储器件的块级上工作。 因此，冗余块可以代替具有比在集成电路存储器件中提供的冗余行和/或列的数量更多的有缺陷的行和/或列的块。 包括多个正常块选择电路，其中相应的一个响应于多个存储单元块中的相应一个的地址产生相应的正常块选择信号。 还包括多个可编程块选择电路，其相应的一个连接在多个正常块选择电路中的相应一个和多个存储单元块中的相应一个。 每个可编程块选择电路包括第一熔丝，其激活阻塞多个正常块选择电路中的相应一个。 每个可编程块选择电路还包括多个第二熔丝，其激活为多个存储单元块中的相应一个块生成替换地址。 还包括多个块禁止电路，其相应的一个连接到多个存储单元块中的相应一个。 多个块禁止电路中的每一个包括熔丝，其激活禁止多个存储单元块中的对应的一个。

公开(公告)号：US09036406B2

公开(公告)日：2015-05-19

申请号：US13832101

申请日：2013-03-15

申请人： Hye-Jin Kim ,  Sang-Kyu Kang ,  Dong-Hyun Sohn ,  Dong-Min Kim ,  Kyu-Chan Lee

发明人： Hye-Jin Kim ,  Sang-Kyu Kang ,  Dong-Hyun Sohn ,  Dong-Min Kim ,  Kyu-Chan Lee

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C5/14

CPC分类号： G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

摘要： A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.

摘要翻译： MRAM包括自旋转移转矩磁随机存取存储器（STT-MRAM）单元的存储单元阵列和通常连接到多个STT-MRAM单元的源极线。 源极线电压发生器响应于外部电源电压产生源极线驱动电压，并将源极线驱动电压提供给源极线。

公开(公告)号：US08310853B2

公开(公告)日：2012-11-13

申请号：US12987539

申请日：2011-01-10

申请人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

发明人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

IPC分类号： G11C5/02

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。