公开(公告)号：US06323702B1

公开(公告)日：2001-11-27

申请号：US09547583

申请日：2000-04-12

申请人： Kyu-chan Lee ,  Nam-jong Kim

发明人： Kyu-chan Lee ,  Nam-jong Kim

IPC分类号： H03K513

CPC分类号： B29C65/348 ,  B29C65/342 ,  B29C65/3464 ,  B29C65/3468 ,  B29C65/7802 ,  B29C66/02241 ,  B29C66/1142 ,  B29C66/301 ,  B29C66/5221 ,  B29C66/72523 ,  B29L2023/22 ,  B29L2024/00 ,  Y10S264/46 ,  Y10T156/1043 ,  Y10T156/1066 ,  B29C65/00

摘要： A signal line drive circuit for a semiconductor device includes a first driver having an input for receiving an input signal and an output, a second driver having an input connected to the output of the first driver and an output connected to a signal line, and a third driver having an input connected to the output of the first driver and an output connected to a point of the signal line. The point of the signal line is spaced from the output of the second driver such that a first load is present between the output of the second driver and the point of the signal line, and such that a second load is present between the point of the signal line and an output of the signal line. The first, second and third drivers each include at least one inverting buffer. The drive circuit reduces a delay time of a signal transmitted through the signal line, and improves the voltage-time slope of the transmitted signal.

摘要翻译： 一种用于半导体器件的信号线驱动电路包括具有用于接收输入信号和输出的输入的第一驱动器，具有连接到第一驱动器的输出的输入端和连接到信号线的输出的第二驱动器，以及 第三驱动器具有连接到第一驱动器的输出的输入端和连接到信号线点的输出。 信号线的点与第二驱动器的输出间隔开，使得第二驱动器的输出端与信号线的点之间存在第一负载，并且使得第二负载存在于 信号线和信号线的输出。 第一，第二和第三驱动器每个包括至少一个反相缓冲器。 驱动电路减少了通过信号线传输的信号的延迟时间，并且提高了发送信号的电压 - 时间斜率。

公开(公告)号：US6005825A

公开(公告)日：1999-12-21

申请号：US178734

申请日：1998-10-27

申请人： Kyu-chan Lee ,  Nam-jong Kim

发明人： Kyu-chan Lee ,  Nam-jong Kim

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/22

摘要： A synchronous semiconductor memory device having a wave pipelining control structure and a method of outputting data therefrom. A register for storing the data output from a memory cell is controlled by a control signal in response to first and second external clock signals. The level transition of the control signal derived from the first clock is delayed, so that data output malfunctioning is prevented even though manufacturing process conditions are changed.

摘要翻译： 一种具有波形流水线控制结构的同步半导体存储器件以及从其输出数据的方法。 用于存储从存储器单元输出的数据的寄存器由响应于第一和第二外部时钟信号的控制信号控制。 从第一时钟导出的控制信号的电平转换被延迟，从而即使改变制造工艺条件，也防止数据输出故障。

公开(公告)号：US6025621A

公开(公告)日：2000-02-15

申请号：US179556

申请日：1998-10-27

申请人： Kyu-chan Lee ,  Keum-yong Kim

发明人： Kyu-chan Lee ,  Keum-yong Kim

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/108 ,  H01L27/105 ,  Y10S257/901

摘要： Integrated circuit memory devices include a semiconductor substrate of first conductivity type (e.g., P-type), a first well region of second conductivity type (e.g., N-type) in the substrate and first and second nonoverlapping sub-well regions of first conductivity type in the first well region. To improve the electrical characteristics of circuits within the memory device, a first semiconductor device is provided in the first sub-well region (which is biased at a back-bias potential (Vbb)) and a second semiconductor device is provided in the second sub-well region (which is biased at a ground or negative supply potential (Vss)). The first semiconductor device is preferably selected from the group consisting of memory cell access transistors, equalization circuits and isolation gates. The second semiconductor device is also preferably selected from the group consisting of column select circuits and sense amplifiers.

摘要翻译： 集成电路存储器件包括第一导电类型的半导体衬底（例如，P型），第二导电类型的第一阱区（例如，N型）以及第一和第二非重叠子阱区 键入第一个井区域。 为了改善存储器件内的电路的电特性，第一半导体器件设置在第一子阱区域中（偏置在背偏电位（Vbb）），第二半导体器件设置在第二子阱 （区域偏置在地或负电位（Vss））。 第一半导体器件优选地选自由存储单元存取晶体管，均衡电路和隔离栅极组成的组。 第二半导体器件还优选地选自列选择电路和读出放大器。

公开(公告)号：US08456397B2

公开(公告)日：2013-06-04

申请号：US12476716

申请日：2009-06-02

申请人： Sung-soo Kim ,  Kyu-chan Lee ,  Hyeong-sik Choi

发明人： Sung-soo Kim ,  Kyu-chan Lee ,  Hyeong-sik Choi

IPC分类号： G09G3/36 ,  G09G5/10

CPC分类号： G09G3/3648 ,  G09G2310/06 ,  G09G2320/0252 ,  G09G2320/0257 ,  G09G2340/16 ,  G09G2360/18

摘要： A display apparatus for calibrating a grayscale data including a timing controller, and a method for driving a panel are provided. A display apparatus includes a timing controller which calibrates the grayscale data of the current frame using the grayscale data of the previous and the current frame and a driving unit which drives a panel using the calibrated grayscale data of the current frame. By generating calibrated grayscale data which are variable according to the change of grayscale, response times of liquid crystal may be improved.

摘要翻译： 提供了用于校准包括定时控制器的灰度数据的显示装置和用于驱动面板的方法。 显示装置包括使用前一帧和当前帧的灰阶数据来校准当前帧的灰阶数据的定时控制器，以及使用当前帧的校准灰度数据来驱动面板的驱动单元。 通过生成根据灰度变化可变的校准灰度数据，可以提高液晶的响应时间。

公开(公告)号：US06175263B1

公开(公告)日：2001-01-16

申请号：US09104857

申请日：1998-06-24

申请人： Kyu-chan Lee ,  Hong-il Yoon

发明人： Kyu-chan Lee ,  Hong-il Yoon

IPC分类号： G05F110

CPC分类号： G05F3/205

摘要： A back bias generator for a semiconductor device improves refresh characteristics, reduces leakage current, and increases back bias supply capacity in a DRAM having a triple well structure by applying a well bias voltage to the bulk of an NMOS transfer transistor. The back bias generator includes a well bias generator that generates the well bias voltage before the pumping voltage is applied to the transfer transistor. The well bias provides a back bias to a parasitic NPN transistor formed in the triple well of the NMOS transfer transistor, thereby preventing leakage through the NPN into the substrate. The well bias is also applied to the bulk of a clamp transistor that initializes a pumping capacitor.

摘要翻译： 用于半导体器件的背偏置发生器通过向NMOS传输晶体管的本体施加阱偏置电压来改善具有三阱结构的DRAM中的刷新特性，减小漏电流并增加背偏置电源容量。 背偏置发生器包括井偏压发生器，其在将泵浦电压施加到转移晶体管之前产生阱偏置电压。 阱偏压为在NMOS传输晶体管的三阱中形成的寄生NPN晶体管提供反偏压，从而防止NPN中漏入衬底。 阱偏压也适用于初始化泵浦电容器的钳位晶体管的大部分。

公开(公告)号：US5701268A

公开(公告)日：1997-12-23

申请号：US701892

申请日：1996-08-23

申请人： Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

发明人： Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： Integrated circuit memory devices include at least first and second memory cells electrically coupled to respective first and second sense bit signal lines of a sense amplifier. The sense amplifier comprises a circuit for amplifying a difference in potential between the first and second sense bit signal lines by driving these lines to respective first and second different potentials. A driving circuit is also provided for simultaneously driving the first and second sense bit signal lines towards the first potential in response to application of a boost control signal. This driving circuit preferably comprises a first capacitor electrically connected in series between the boost control input and the first sense bit signal line and a second capacitor electrically connected in series between the boost control input and the second sense bit signal line. The boost control signal is established at the first potential to drive both the sense bit signal lines from different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) towards the first potential, prior to amplification of the difference in potential between the first and second sense bit signal lines by the sense amplifier. The present invention enables the sense amplifier to operate in an environment where the power supply voltage (e.g., VCC) is reduced and the different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) to be amplified are initially established at potentials below the normal sensitivity of the sense amplifier.

摘要翻译： 集成电路存储器件包括电耦合到读出放大器的相应第一和第二感测位信号线的至少第一和第二存储器单元。 感测放大器包括用于通过将这些线驱动到相应的第一和第二不同电位来放大第一和第二感测位信号线之间的电位差的电路。 还提供驱动电路，用于响应于施加升压控制信号，同时将第一和第二感测位信号线驱动朝向第一电位。 该驱动电路优选地包括串联电连接在升压控制输入和第一感测位信号线之间的第一电容器和串联电连接在升压控制输入和第二感测位信号线之间的第二电容器。 升压控制信号被建立在第一电位，以驱动来自不同中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E，fra 1/2 + EE VCC）的感测位信号线朝着第一 在由感测放大器放大第一和第二感测位信号线之间的电位差之前的电位。 本发明使得读出放大器能够在电源电压（例如，VCC）减小的环境中工作，并且不同的中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E， + EE VCC）最初建立在低于读出放大器正常灵敏度的电位。

公开(公告)号：US06269046B1

公开(公告)日：2001-07-31

申请号：US09533530

申请日：2000-03-23

申请人： Kyu-chan Lee ,  Sang-man Byun

发明人： Kyu-chan Lee ,  Sang-man Byun

IPC分类号： G11C800

CPC分类号： G11C8/10

摘要： The semiconductor memory device includes a power supply voltage (Vcc) applied to the semiconductor device, a row controller for generating an output signal in response to a control signal representing one of a normal operation state and a stand-by state, and a plurality of row decoders connected between the row controller and a plurality of word lines. Each row decoder activates a corresponding word line in response to the output signal from the row controller and a row address signal from an external source, and the output signal of the row controller is a high voltage or a ground voltage when the plurality of row decoders are in a normal operation state or in a stand-by state, respectively. The semiconductor memory device also includes a column controller for generating an output signal in response to a first control signal representing one of a normal operation state and a stand-by state and a plurality of column decoders connected between the column controller and a plurality of column selection lines. Each column decoder activates a corresponding column selection line in response to the output signal from the column controller, a column address signal, and a second control signal, and the output signal of the column controller is an internal supply voltage or the ground voltage when the plurality of column decoders are in a normal operation state or in a stand-by state, respectively. The semiconductor memory device does not generate leakage current in a stand-by state.

摘要翻译： 半导体存储器件包括施加到半导体器件的电源电压（Vcc），响应于表示正常工作状态和待机状态之一的控制信号产生输出信号的行控制器，以及多个 连接在行控制器和多个字线之间的行解码器。 响应于来自行控制器的输出信号和来自外部源的行地址信号，每行解码器激活相应的字线，并且当多行行解码器时，行控制器的输出信号为高电压或接地电压 分别处于正常操作状态或待机状态。 半导体存储器件还包括列控制器，用于响应于表示正常操作状态和待机状态之一的第一控制信号和连接在列控制器与多列之间的多个列解码器产生输出信号 选线。 响应于来自列控制器的输出信号，列地址信号和第二控制信号，每列解码器激活相应的列选择线，并且列控制器的输出信号是内部电源电压或接地电压 多个列解码器分别处于正常操作状态或处于待机状态。 半导体存储器件在待机状态下不产生漏电流。

公开(公告)号：US5892386A

公开(公告)日：1999-04-06

申请号：US760250

申请日：1996-12-05

申请人： Kyu-chan Lee ,  Jung-hwa Lee ,  Seung-moon Yoo

发明人： Kyu-chan Lee ,  Jung-hwa Lee ,  Seung-moon Yoo

IPC分类号： G11C11/401 ,  G11C5/14 ,  G11C29/04 ,  G11C29/50 ,  H01L21/822 ,  H01L27/04 ,  H03K3/037

CPC分类号： G11C29/50 ,  G11C11/401

摘要： An internal power control circuit for a semiconductor device allows easy testing of the internal circuit blocks or memory arrays at various voltage levels. In the semiconductor device, internal voltage switching circuits connected between the internal power supply line and each array power supply line are switched ON or OFF according to signals applied to control pads coupled to each internal voltage switching circuit. During normal operation, a power voltage generated by the internal voltage generator is applied through an internal power supply line to each array power supply line coupled to the internal circuit blocks. During a test operation, different power voltages may be applied to the control pads to selectively decouple individual array power supply lines from the internal power supply line, and selectively couple the power voltages applied to the control pads to the corresponding array power supply lines and internal circuit blocks.

摘要翻译： 用于半导体器件的内部功率控制电路允许在各种电压电平下容易地测试内部电路块或存储器阵列。 在半导体器件中，连接在内部电源线和每个阵列电源线之间的内部电压切换电路根据施加到耦合到每个内部电压切换电路的控制焊盘的信号而被接通或断开。 在正常操作期间，内部电压发生器产生的电力电压通过内部电源线施加到耦合到内部电路块的每个阵列电源线。 在测试操作期间，可以将不同的电源电压施加到控制焊盘，以选择性地将各个阵列电源线与内部电源线分离，并且将施加到控制焊盘的电力电压选择性地耦合到相应的阵列电源线和内部 电路块。

公开(公告)号：US06233196B1

公开(公告)日：2001-05-15

申请号：US09351718

申请日：1999-07-12

申请人： Kyu-chan Lee

发明人： Kyu-chan Lee

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C5/025 ,  G11C8/10

摘要： Multi-bank integrated circuit memory devices include a plurality of banks of memory cells that are divided into pairs of sub-banks of memory cells. The sub-banks of memory cells are arranged in a plurality of rows and columns of sub-banks of memory cells. The pairs of sub-banks extend diagonally relative to the plurality of rows and columns of sub-banks of memory cells. The pairs of sub-banks of the respective banks preferably are adjacent one another and extend diagonally relative to the plurality of rows and columns of sub-banks of memory cells. By providing diagonally extending sub-banks, the row address lines that extend between respective sub-banks of each bank may occupy reduced area. More specifically, row address lines that extend between pairs of sub-banks in same adjacent rows and same adjacent columns can cross over one another to thereby allow reduced area.

摘要翻译： 多组集成电路存储器件包括被划分成存储单元的子组对的多个存储单元组。 存储单元的子库被布置在多个存储单元子行的行和列中。 这些子库对相对于存储单元的子行的多个行和列倾斜地延伸。 各个分组的子组对优选地彼此相邻并且相对于存储单元的子行的多个行和列倾斜延伸。 通过提供对角延伸的子库，在每个存储体的相应子存储体之间延伸的行地址行可以占用减少的区域。 更具体地说，在相同的相邻行和相邻的相邻列之间延伸的子行对之间的行地址行可以彼此交叉，从而允许减少的区域。

公开(公告)号：US5770957A

公开(公告)日：1998-06-23

申请号：US825227

申请日：1997-03-19

申请人： Kyu-chan Lee

发明人： Kyu-chan Lee

IPC分类号： G06F1/32 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  H03B1/00

CPC分类号： G11C7/06

摘要： A signal generator produces enable signals for bitline sense amplifiers in a semiconductor device. The signal generator includes a first driving element for producing a first enable signal at a first output line in response to first and second control signals, a second driving element for producing a second enable signal at a second output line in response to inverted signals of the first and second control signals, and an equalizing element connected between the first output line and the second output line for equalizing the first and second output lines in response to a third control signal. A control signal generating element generates the first, second, and third control signals, and inverted signals thereof, in response to predetermined input signals. The DC current generated from an output driver and the charging and discharging current of output loading can be reduced, to thereby reduce power consumption. Also, when the output signals are applied as enable signals of bitline sense amplifiers, an initial invalid sensing the bitline sense amplifier circuits can be avoided.

摘要翻译： 信号发生器在半导体器件中产生用于位线读出放大器的使能信号。 信号发生器包括：第一驱动元件，用于响应于第一和第二控制信号在第一输出线处产生第一使能信号;第二驱动元件，用于响应于第二输出线的反相信号在第二输出线处产生第二使能信号 第一和第二控制信号，以及连接在第一输出线和第二输出线之间的均衡元件，用于响应于第三控制信号对第一和第二输出线进行均衡。 控制信号产生元件响应于预定的输入信号产生第一，第二和第三控制信号及其反相信号。 可以减少从输出驱动器产生的直流电流和输出负载的充放电电流，从而降低功耗。 此外，当输出信号被施加作为位线读出放大器的使能信号时，可以避免初始无效感测位线读出放大器电路。