公开(公告)号：US07688630B2

公开(公告)日：2010-03-30

申请号：US12370810

申请日：2009-02-13

Applicant: Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

Inventor： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract translation: 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US20090190400A1

公开(公告)日：2009-07-30

申请号：US12417224

申请日：2009-04-02

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

Abstract: A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

Abstract translation: 具有单级单元和多级单元的非易失性存储器阵列。 在一个实施例中，单电平和多电平电池沿着每个位线交替。 一个替代实施例沿着位线和字线交替单电层和多电平单元，使得没有单层单元与字线或位线方向上的另一单级单元相邻。

公开(公告)号：US20070268775A1

公开(公告)日：2007-11-22

申请号：US11436352

申请日：2006-05-18

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C8/00 ,  G11C11/34 ,  G11C16/04

CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C16/0483 ,  G11C16/12 ,  G11C2207/229

Abstract: The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.

Abstract translation: 本发明提供了方法和装置。 NAND闪存器件以第一频率接收命令和地址信号，并以大于第一频率的第二频率接收数据信号。

公开(公告)号：US07251206B2

公开(公告)日：2007-07-31

申请号：US10786173

申请日：2004-02-26

Applicant: Chang-hoon Baek ,  Chul-ho Jeon ,  Seung-man Han ,  Sung-du Kwon

Inventor： Chang-hoon Baek ,  Chul-ho Jeon ,  Seung-man Han ,  Sung-du Kwon

IPC: G11B7/00

CPC classification number: G11B19/26 ,  G11B7/005 ,  G11B19/125

Abstract: An optical signal converter and a method or controlling an amplification gain according to a rotating speed of an optical disc. An optical signal detector detects an optical signal reflected from an optical disc in a reproduction mode and converts the detected optical signal into an electrical signal. A gain control signal generator generates a gain control signal when a voltage level of a driving signal used to drive the optical disc exceeds a maximum output voltage of the optical signal converter. A gain switcher selects an amplification gain of the optical signal converter in response to the gain control signal and an external control signal. A signal amplifier amplifies a signal output from the optical signal detector in response to an output signal of the gain switcher.

Abstract translation: 光信号转换器和方法或根据光盘转速来控制放大增益。 光信号检测器以再现模式检测从光盘反射的光信号，并将检测到的光信号转换为电信号。 当用于驱动光盘的驱动信号的电压电平超过光信号转换器的最大输出电压时，增益控制信号发生器产生增益控制信号。 增益切换器响应于增益控制信号和外部控制信号选择光信号转换器的放大增益。 信号放大器响应于增益切换器的输出信号，放大从光信号检测器输出的信号。

公开(公告)号：US07006398B1

公开(公告)日：2006-02-28

申请号：US10977309

申请日：2004-10-29

Applicant: Sei-Seung Yoon ,  Jin-Man Han ,  Seong-Ook Jung

Inventor： Sei-Seung Yoon ,  Jin-Man Han ,  Seong-Ook Jung

IPC: G11C11/00

CPC classification number: H01L27/11 ,  G11C11/39

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract translation: 本文公开了一种包括用于解析由存储器单元产生的数据信号的读出放大器的感测电路。 感测电路包括用于接收数据信号的位线，耦合到位线并被配置为对位线预充电的第一预充电器件，用于提供耦合到位线的偏置并被配置为提供 偏置到位线，以及被配置为至少一个预定电平的参考节点。 在一个实施例中，预定电平等于诸如地电位的低电位，而在另一实施例中等于诸如V DD的高电位。 一个或多个开关装置允许激活或去激活预充电装置，允许将位线预充电到特定电位，感测电路快速而准确地确定逻辑状态“1”或“0”是否为 应用于位线。

公开(公告)号：US6147527A

公开(公告)日：2000-11-14

申请号：US136871

申请日：1998-08-19

Applicant: Jung-Bae Lee ,  Sung-Geun Lee ,  Jing-Man Han

Inventor： Jung-Bae Lee ,  Sung-Geun Lee ,  Jing-Man Han

IPC: G11C11/407 ,  G06F1/04 ,  G06F1/10 ,  G11C7/22 ,  G11C11/34 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087 ,  H04L7/033 ,  H03K5/14

CPC classification number: G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03K5/133 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/087 ,  H04L7/0337

Abstract: An internal clock generator including a switching controller interposed between a digital delay locked loop and an externally generated clock signal. The switching controller reduces current consumptions starting from a next cycle when an external clock and an internal clock are in phase. Further, when the external clock and the internal clock are in phase, driving of the unnecessary elements is suppressed, thereby reducing the current consumption in the internal clock generator.

Abstract translation: 内部时钟发生器，其包括插入在数字延迟锁定环和外部产生的时钟信号之间的开关控制器。 当外部时钟和内部时钟同相时，开关控制器可以从下一个周期开始降低电流消耗。 此外，当外部时钟和内部时钟同相时，不必要元件的驱动被抑制，从而降低了内部时钟发生器的电流消耗。

公开(公告)号：US6130447A

公开(公告)日：2000-10-10

申请号：US61390

申请日：1998-04-16

Applicant: Jin-man Han

Inventor： Jin-man Han

IPC: G11C11/407 ,  H01L23/528 ,  H01L27/10 ,  H01L29/76

CPC classification number: H01L23/5286 ,  H01L2924/0002

Abstract: At least two spaced apart control lines are located between adjacent spaced apart power lines on a memory cell array of an integrated circuit memory device. The spaced apart power lines preferably are wider than the spaced apart control lines, and the space between adjacent control lines preferably is equal to the space between a power line and an adjacent control line. Accordingly, the width of the power lines can be increased without requiring an increase in the size of the integrated circuit memory.

Abstract translation: 至少两个间隔开的控制线位于集成电路存储器件的存储单元阵列上相邻间隔开的电源线之间。 间隔开的电力线优选地比间隔开的控制线宽，并且相邻控制线之间的空间优选地等于电力线和相邻控制线之间的空间。 因此，可以增加电力线的宽度，而不需要增加集成电路存储器的尺寸。

公开(公告)号：US6097649A

公开(公告)日：2000-08-01

申请号：US088426

申请日：1998-06-01

Applicant: Paul M-Bhor Chiang ,  Jin-Man Han ,  Hung-Mao Lin

Inventor： Paul M-Bhor Chiang ,  Jin-Man Han ,  Hung-Mao Lin

IPC: G11C11/406 ,  G11C7/00

CPC classification number: G11C11/406

Abstract: A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference voltage. Then at least one of a plurality of word lines and at least one of a plurality of reference word lines are selected. Next, the sense amplifier is activated such that either the plurality of bit lines or the plurality of complementary bit lines discharges to a voltage of logic low. This discharge creates a voltage difference between the plurality of bit lines and the plurality of complementary bit lines. The resulting voltage on the bit lines is restored to the memory cells on the selected word lines. Then, the plurality of bit lines and the plurality of complementary bit lines are restored to the reference voltage. This method and structure allows the use of a logic high voltage lower than 2.0 V without compromising the reliability of the sense amplifier. The implementation of the method and structure of the present invention is cost effective and practical for most if not all DRAM applications.

Abstract translation: 提供了一种用于在计算机存储器结构中具有高逻辑高电压的刷新操作的方法和结构。 该方法和系统首先将多个位线和多个互补位线预充电到高于参考电压的电压。 然后，选择多个字线和至少一个参考字线中的至少一个。 接下来，感测放大器被激活，使得多个位线或多个互补位线放电到逻辑低电压。 该放电在多个位线和多个互补位线之间产生电压差。 位线上产生的电压恢复到所选字线上的存储单元。 然后，将多条位线和多条互补位线恢复到参考电压。 该方法和结构允许使用低于2.0V的逻辑高电压，而不损害读出放大器的可靠性。 本发明的方法和结构的实现对于大多数（如果不是全部）DRAM应用是成本有效的和实用的。

公开(公告)号：US5812466A

公开(公告)日：1998-09-22

申请号：US724798

申请日：1996-10-02

Applicant: Jung-Hwa Lee ,  Jin-Man Han ,  Dong-Il Seo

Inventor： Jung-Hwa Lee ,  Jin-Man Han ,  Dong-Il Seo

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/70

Abstract: The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't care," and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line. The column redundancy circuit includes: transmitting means comprised of the data input/output lines for transmitting the data of the memory cell; column decoder and input/output control circuits connected to the transmitting means and decoding a column address input to input data; a circuit connected to the transmitting means and outputting a given signal to the column decoder and input/output control circuits in response to a plurality of output signals output from fuses and a signal for controlling the transmitting means; a plurality of decoded fuse circuits, the levels of which are determined by one fuse connected to the circuit; multiplexers for selectively transmitting data from one of the data input/output lines to a specific data bus line among a plurality of data bus lines; and a decoding circuit which receives the outputs of the decoded fuse circuits and generates a redundancy signal.

Abstract translation: 本发明涉及一种结合使用解码保险丝的列冗余电路的半导体存储器件。 当地址输入为“无关”时，列冗余电路能够在存储器操作的并行测试模式下指定修复的地址，并且在使用一列选择的多输入/输出存储器架构中特别有用 每个I / O线。 列冗余电路包括：发送装置，包括用于发送存储单元的数据的数据输入/输出线; 列解码器和连接到发送装置的输入/输出控制电路，并且将输入的列地址解码为输入数据; 连接到发送装置的电路，响应于从保险丝输出的多个输出信号和用于控制发送装置的信号，将给定信号输出到列解码器和输入/输出控制电路; 多个解码熔丝电路，其电平由连接到电路的一个熔丝确定; 多路复用器，用于选择性地将数据从数据输入/输出线之一发送到多条数据总线之间的特定数据总线; 以及解码电路，其接收解码的熔丝电路的输出并产生冗余信号。

公开(公告)号：US5808957A

公开(公告)日：1998-09-15

申请号：US632594

申请日：1996-04-15

Applicant: Jung-hwa Lee ,  Jin-man Han ,  Se-jin Jeong

Inventor： Jung-hwa Lee ,  Jin-man Han ,  Se-jin Jeong

IPC: G11C11/413 ,  G11C8/06 ,  G11C11/407 ,  G11C11/408 ,  G11C8/00

CPC classification number: G11C8/06

Abstract: Address buffers of a semiconductor memory device have a switching section for switching into each other transmission routes of first and second address signals input from outside in response to predetermined control signals. The signals allow input of the address signals and set the operating mode of the semiconductor memory device.

Abstract translation: 半导体存储器件的地址缓冲器具有用于响应于预定的控制信号而从外部输入的第一和第二地址信号彼此切换的切换部分。 信号允许输入地址信号并设置半导体存储器件的工作模式。