公开(公告)号：US09627879B2

公开(公告)日：2017-04-18

申请号：US13990936

申请日：2011-12-02

Applicant: Marco Zamprogno ,  Alberto Minuti ,  Germano Nicollini

Inventor： Marco Zamprogno ,  Alberto Minuti ,  Germano Nicollini

IPC: H02H3/20 ,  H02J1/10 ,  H02J7/00 ,  H02J7/34

CPC classification number: H02H3/20 ,  H02H3/207 ,  H02J1/10 ,  H02J7/0031 ,  H02J7/345

Abstract: An apparatus (100) for protecting a circuit (200) from an input volume comprises a switchable element (10) arranged to couple the input voltage (VIN) to the circuit (200) in response to a first control signal (DRV1) having a first value and to decouple the input voltage (VIN) from the circuit (200) in response to the first control signal (DRV1) having a second value. A monitor stage (20) compares a monitored voltage (VMON) to a threshold (VIN). A controller (30) provides the first control signal (DRV1) to the switchable element (10), the first control signal (DRV1) having the first value when the monitored voltage (VMON) is on one side of the threshold (VTH) and the second value when the monitored voltage (VMON) is on the other side of the threshold (VTH), wherein the first value is independent of the input voltage (VIN) and the second value is equal to the input voltage (VIN).

公开(公告)号：US20090219085A1

公开(公告)日：2009-09-03

申请号：US12395409

申请日：2009-02-27

Applicant: Marco Zamprogno ,  Pierangelo Confalonieri ,  Alberto Minuti

Inventor： Marco Zamprogno ,  Pierangelo Confalonieri ,  Alberto Minuti

IPC: G06G7/12

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit for conversion from differential to single-ended includes a differential amplifier stage and first and second buffer circuits. The differential amplifier stage includes a first and a second input; and a first and a different second charging circuit that can be operatively coupled, respectively, with an output of the conversion circuit and with an auxiliary output. Each of the first and second buffer circuits is functionally arranged between one of said outputs and between one of said charging circuits. The buffer circuits being configured so as to substantially equalize relative impedances seen towards said outputs.

Abstract translation: 用于从差分到单端转换的电路包括差分放大器级和第一和第二缓冲电路。 差分放大器级包括第一和第二输入; 以及可以分别与转换电路的输出和辅助输出可操作地耦合的第一和第二充电电路。 第一和第二缓冲电路中的每一个功能地布置在所述输出之一和所述充电电路之一之间。 缓冲电路被配置为基本上相等于所述输出端所看到的相对阻抗。

公开(公告)号：US20090212830A1

公开(公告)日：2009-08-27

申请号：US12391574

申请日：2009-02-24

Applicant: Marco Zamprogno ,  Germano Nicollini ,  Alberto Minuti

Inventor： Marco Zamprogno ,  Germano Nicollini ,  Alberto Minuti

IPC: H03K3/00

CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

Abstract: An integrated buffer device for a switched capacitance circuit having a buffer with an output for an output voltage dependent upon an input voltage that can be supplied by a source to the buffer device; a capacitive switching component that can be switched between a first and second condition and connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; the capacitive switching component provided with a terminal having an associated stray capacitance; a charging and discharging device configured to pre-charge the stray capacitance at a reference voltage before taking up the second condition and to pre-discharge the stray capacitance before taking up the first condition.

Abstract translation: 一种用于开关电容电路的集成缓冲装置，具有缓冲器，该缓冲器具有取决于可由缓冲装置提供的输入电压的输出电压的输出; 电容开关部件，其可以在第一和第二状态之间切换并分别连接到源极和缓冲器，以将输入电压传递到输出端; 所述电容开关元件设置有具有相关杂散电容的端子; 充电和放电装置，其被配置为在占用所述第二状态之前以参考电压对所述寄生电容进行预充电，并且在占用所述第一状态之前对所述杂散电容进行预放电。

公开(公告)号：US20090033531A1

公开(公告)日：2009-02-05

申请号：US12172692

申请日：2008-07-14

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Riccardo Martignone

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Riccardo Martignone

IPC: H03M1/66 ,  H03M1/00

CPC classification number: H03M1/0648 ,  H03M1/687 ,  H03M1/747

Abstract: A current steering digital-analog converter for converting a digital code into an analog signal, the converter including a substrate of semiconductor material, an array of current generators integrated in the substrate, a common summation node and switches controllable on the basis of the digital code for connecting and disconnecting the current generators to and from the common summation node. The current generators are adapted to provide the common summation node with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator of the array of generators. The current generator is divided into a base number of modular current generation elements in parallel to one another at least equal to two.

Abstract translation: 一种用于将数字代码转换为模拟信号的电流转向数模转换器，所述转换器包括半导体材料的衬底，集成在衬底中的电流发生器的阵列，公共求和节点和基于数字代码可控的开关 用于将当前发生器连接到和从公共求和节点断开连接。 电流发生器适于根据与发电机阵列的电流发生器提供给求和节点的单位电流值相比的功率，为公共求和节点提供具有多个值的电流。 电流发生器被分成基本数量的模块化电流产生元件，彼此平行至少等于2。

公开(公告)号：US20080221823A1

公开(公告)日：2008-09-11

申请号：US12035308

申请日：2008-02-21

Applicant: Pierangelo Confalonieri ,  Riccardo Martignone ,  Marco Zamprogno

Inventor： Pierangelo Confalonieri ,  Riccardo Martignone ,  Marco Zamprogno

IPC: G01R35/00

CPC classification number: H03H1/02 ,  H03H7/0153 ,  H03H2210/021 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2210/043

Abstract: A calibration circuit calibrates an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance. The calibration circuit outputs a calibration signal carrying information for calibrating the capacitor and includes a calibration loop. The calibration circuit includes: a controllable capacitance unit suitable to receive a control signal and including at least one array of switched capacitors that can be activated by the control signal, the unit being such as to output a first signal characterized by a parameter depending on the amount of capacitance of the array activated by the control signal; a comparison unit suitable to receive the first signal to assess whether the parameter meets a preset condition and to output a comparison signal representative of the assessment result; a control and timing logic unit suitable to receive the comparison signal to change this control signal based on the comparison signal, characterized in that the first signal is a logic signal and the parameter is a time parameter of the first signal.

Abstract translation: 校准电路根据可调电容校准具有时间常数的电路的可调电容。 校准电路输出一个载有用于校准电容器的信息的校准信号，并包括校准环路。 所述校准电路包括：可控电容单元，其适于接收控制信号并且包括可被所述控制信号激活的至少一个开关电容阵列，所述单元使得输出第一信号，所述第一信号的特征在于根据 由控制信号激活的阵列的电容量; 适于接收第一信号以评估参数是否满足预置条件并输出表示评估结果的比较信号的比较单元; 适于接收比较信号以根据比较信号改变该控制信号的控制和定时逻辑单元，其特征在于，第一信号是逻辑信号，该参数是第一信号的时间参数。

公开(公告)号：US20050231412A1

公开(公告)日：2005-10-20

申请号：US11097456

申请日：2005-04-01

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03M1/002 ,  H03M1/462

Abstract: The described analog-digital converter comprises quantization means having an input for receiving an analog quantity to be converted, a register having an output for providing a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means connected to the quantization means, the register and the timing pulse generator and capable of responding to a conversion request signal by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register the digital quantity to be provided at the output. With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator, which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input and the logic means are capable of generating a stop signal of the oscillator and comprise means for generating the binary signal to be applied to the activation input of the oscillator. This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal and the stop signal of the oscillator.

Abstract translation: 所描述的模拟数字转换器包括具有用于接收要转换的模拟量的输入的量化装置，具有用于提供与模拟量相对应的数字量的输出的寄存器，连接到量化装置的定时脉冲发生器和逻辑装置， 寄存器和定时脉冲发生器，并且能够通过激活量化装置来响应转换请求信号，以使得它们执行由定时脉冲定时的预定操作并将其加载到寄存器中以在 输出。 为了允许转换器即使在系统时钟不可用的情况下也能够运行，包含在转换器的其余部分的集成电路中的定时脉冲发生器包括能够被二进制数进行启动/停止的振荡器 施加到其激活输入的信号，并且逻辑装置能够产生振荡器的停止信号，并且包括用于产生要施加到振荡器的激活输入的二进制信号的装置。 该信号分别响应于转换请求信号和振荡器的停止信号而分别对应于振荡器的激活和去激活的第一或第二二进制状态。

公开(公告)号：US06621444B1

公开(公告)日：2003-09-16

申请号：US10174501

申请日：2002-06-17

Applicant: Pierangelo Confalonieri ,  Angelo Nagari ,  Marco Zamprogno

Inventor： Pierangelo Confalonieri ,  Angelo Nagari ,  Marco Zamprogno

IPC: H03M112

CPC classification number: H03M1/002 ,  H03M1/466 ,  H03M1/804

Abstract: A switched capacitor digital-to-analog converter includes a first voltage generator for providing first and second reference voltages, a second voltage generator for providing third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, and an array of binary weighted capacitors. Each capacitor has a first electrode connected to a common circuit node, which is connected to a converter output terminal and a second electrode selectively connected, through an associated first switching circuit, to either one of the first and second reference voltages or, through an associated second switching circuit, to either one of the third and fourth reference voltages. The converter includes a circuit for monitoring the values of each bit of input digital codes, and a control circuit coupled to the first and second switching circuits to open or close selectively during a bit clock period the connections to the first, second, third, and fourth voltages according to the following criterion: when a bit value of the current input digital code Bj is equal to the corresponding bit value of the previous input digital code Bj−1, the first switching circuit is enabled and the second switching circuit is disabled during the whole bit clock period, and when the monitoring circuit detects a bit value of a current input digital code Bj to be different from the corresponding bit value of the previous input digital code Bj−1, the first switching circuit is disabled and the second switching circuit is enabled during a starting time portion of the bit clock period, while the first switching circuit is enabled and the second switching circuit is disabled during the remaining portion of the bit clock period.

Abstract translation: 开关电容器数模转换器包括用于提供第一和第二参考电压的第一电压发生器，用于提供第三和第四参考电压的第二电压发生器，所述第三和第四参考电压被选择以匹配第一和第二参考电压的预定设计值， 的二进制加权电容。 每个电容器具有连接到公共电路节点的第一电极，其连接到转换器输出端子和通过相关联的第一开关电路选择性地连接到第一和第二参考电压中的任一个的第二电极，或者通过相关联的 第二开关电路，到第三和第四参考电压中的任一个。 转换器包括用于监视每一位输入数字代码的值的电路，以及耦合到第一和第二开关电路的控制电路，用于在位时钟周期期间有选择地打开或关闭与第一，第二，第三和第 第四电压根据以下标准：当当前输入数字码Bj的位值等于先前输入数字码Bj-1的相应位值时，第一开关电路被使能，并且第二开关电路在 整个位时钟周期，并且当监视电路检测到当前输入数字码Bj的比特值与先前输入数字码Bj-1的对应比特值不同时，第一切换电路被禁用，第二切换 在位时钟周期的起始时间部分期间使能电路，而第一开关电路被使能并且第二开关电路在重新启动期间被禁止 占位时钟周期的一部分。

公开(公告)号：US20130214948A1

公开(公告)日：2013-08-22

申请号：US13822347

申请日：2011-09-08

Applicant: Germano Nicollini ,  Alberto Minuti ,  Marco Zamprogno

Inventor： Germano Nicollini ,  Alberto Minuti ,  Marco Zamprogno

IPC: H03M1/12

CPC classification number: H03M1/124 ,  G11C27/026 ,  H03F3/45475 ,  H03F3/45986 ,  H03F2203/45512 ,  H03F2203/45536

Abstract: A single-ended to differential buffer circuit is is disclosed, adapted to couple at least an input analog signal to a receiving circuit. The buffer circuit comprises an output section comprising a differential amplifier having a first and a second input, a first and a second output. The buffer circuit further comprises an input section comprising a first and a second switched capacitor, each adapted to sample said input analog signal and having a first side and a second side, the first sides of the first and second switched capacitors being controllably connectable/disconnectable to/from said first and second outputs respectively. In the buffer circuit the second sides of said first and second switched capacitors are controllably connectable/disconnectable to/from said first and second inputs of the differential amplifier respectively. Moreover, in the buffer circuit the second sides of the first and second switched capacitors are controllably connectable/disconnectable to/from said second output and said first output respectively. A method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs is also disclosed.

Abstract translation: 公开了适用于将至少一个输入模拟信号耦合到接收电路的单端到差分缓冲电路。 缓冲电路包括输出部分，其包括具有第一和第二输入的差分放大器，第一和第二输出。 缓冲电路还包括一个输入部分，它包括一个第一和第二个开关电容器，每个开关电容器适于对所述输入模拟信号进行采样并具有第一侧和第二侧，第一和第二开关电容器的第一侧是可控地可连接/可断开的 分别来自所述第一和第二输出。 在缓冲电路中，所述第一和第二开关电容器的第二侧分别与差分放大器的第一和第二输入端分别可控地连接/断开。 此外，在缓冲电路中，第一和第二开关电容器的第二侧分别可控地与所述第二输出端和所述第一输出端连接/断开。 还公开了一种用于将至少单端输入模拟信号耦合到具有差分输入的接收电路的方法。

公开(公告)号：US07425857B2

公开(公告)日：2008-09-16

申请号：US11055564

申请日：2005-02-09

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Federico Garibaldi

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Federico Garibaldi

IPC: H03H11/26

CPC classification number: H03H11/26 ,  H03K5/04 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00123 ,  H03K2005/00143 ,  H03K2005/00156 ,  H03K2005/00195

Abstract: A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.

Abstract translation: 时间延迟逻辑包括具有逆变器的第一级，连接到逆变器的输入端的电容器，恒定电流发生器和由输入脉冲控制的电子开关。 电容器开始在输入脉冲的预定边沿充电，并将逆变器的输入端从第一电压（接地）转换到逆变器的开关阈值电压，从而在逆变器的输出端上获得 具有如参照输入脉冲的预定边缘具有取决于反相器阈值的延迟时间的边缘的脉冲。 电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级中的一级的反相器。

公开(公告)号：US20080036641A1

公开(公告)日：2008-02-14

申请号：US11832946

申请日：2007-08-02

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC: H03M1/12

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

Abstract: An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.

Abstract translation: 用于将模拟信号转换为数字输出代码的模拟/数字转换器包括具有分段阵列的本地数字模拟转换器。 分段阵列包括转换元件的上段和下段，其选择性地由相应的数字命令代码操作，以分别根据二进制加权贡献来改变第一和第二公共节点的电压和第二公共节点的电压。 逻辑单元根据用于产生数字输出代码的逐次逼近技术产生用于控制本地数字/模拟转换器的数字命令代码。 转换器包括再分配器，用于在使用在上段中提供的至少一个辅助转换元件的同时修改用于在下段和上段之间重新分配修改的命令代码的命令代码。