公开(公告)号：US20060170453A1

公开(公告)日：2006-08-03

申请号：US11368012

申请日：2006-03-03

Applicant: Jared Zerbe ,  Bruno Garlepp ,  Pak Chau ,  Kevin Donnelly ,  Mark Horowitz ,  Stefanos Sidiropoulos ,  Billy Garrett ,  Carl Werner

Inventor： Jared Zerbe ,  Bruno Garlepp ,  Pak Chau ,  Kevin Donnelly ,  Mark Horowitz ,  Stefanos Sidiropoulos ,  Billy Garrett ,  Carl Werner

IPC: H03K19/173 ,  G06F7/38

CPC classification number: H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

Abstract: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

公开(公告)号：US06378020B2

公开(公告)日：2002-04-23

申请号：US09545648

申请日：2000-04-10

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1300

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system and an integrated circuit device therefor. The integrated circuit device comprises output driver circuitry to output data onto a first external signal line. The output driver circuitry outputs a first portion of data in response to a rising edge transition of a first external clock signal. The output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal. The integrated circuit device may further include input receiver circuitry to sample data from a second external signal line. The input receiver circuitry samples a first portion of data in response to a rising edge transition of a second external clock signal. The input receiver circuitry samples a second portion of data in response to a falling edge transition of the second external clock signal.

Abstract translation: 一种系统及其集成电路装置。 集成电路装置包括输出驱动器电路以将数据输出到第一外部信号线上。 输出驱动器电路响应于第一外部时钟信号的上升沿转变而输出数据的第一部分。 输出驱动器电路响应于第一外部时钟信号的下降沿转变而输出数据的第二部分。 集成电路装置还可以包括用于从第二外部信号线采样数据的输入接收器电路。 输入接收器电路响应于第二外部时钟信号的上升沿转变而采样数据的第一部分。 响应于第二外部时钟信号的下降沿转换，输入接收机电路对第二部分数据进行采样。

公开(公告)号：US06304937B1

公开(公告)日：2001-10-16

申请号：US09669295

申请日：2000-09-25

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1300

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of operation of a memory controller device, the method of operation comprises issuing a write request to a memory device synchronously with respect to an external clock signal, wherein in response to the write request, a memory device inputs first and second portions of data. The method of operation further includes outputting the first portion of data synchronously with respect to a first edge transition of an external clock signal; and outputting the second portion of data from the bus synchronously with respect to a second edge transition of the external clock signal. The first and second edge transitions of the external clock signal are of transitions of the same clock cycle.

Abstract translation: 一种存储器控制器设备的操作方法，所述操作方法包括相对于外部时钟信号向存储器件发送写入请求，其中响应于写入请求，存储器件输入数据的第一和第二部分 。 所述操作方法还包括相对于外部时钟信号的第一边沿转换同步地输出数据的第一部分; 并且相对于所述外部时钟信号的第二边缘转换同步地从所述总线输出所述第二部分数据。 外部时钟信号的第一和第二边缘跃迁是相同时钟周期的转变。

公开(公告)号：US06266285B1

公开(公告)日：2001-07-24

申请号：US09566551

申请日：2000-05-08

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C700

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of operation of a memory device. The memory device including a section of memory having a plurality of memory cells. The method of operation comprises receiving a request for a write operation and sampling a first portion of data after a delay time transpires in response to the request for a write operation. A method of controlling the memory device comprises issuing a request for a write operation to the memory device. The memory device samples data after a number of clock cycles of the external clock signal transpire in response to the request. The method of controlling also comprises issuing a first portion of data to the memory device after the number of clock cycles of the external clock signal transpire.

Abstract translation: 一种存储器件的操作方法。 该存储装置包括具有多个存储单元的一部分存储器。 操作方法包括响应于写入操作的请求，在延迟时间发生之后接收对写操作的请求并对数据的第一部分进行采样。 一种控制存储器件的方法包括向存储器件发出对写入操作的请求。 存储器件响应于该请求，在外部时钟信号的多个时钟周期发生之后对数据进行采样。 控制方法还包括在外部时钟信号的时钟周期数量发生之后向存储器件发出第一部分数据。

公开(公告)号：US06185644B2

公开(公告)日：2001-02-06

申请号：US09487524

申请日：2000-01-19

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1300

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system having a master device and a plurality of memory subsystems, including first and second memory subsystems coupled to a first bus. Each memory subsystem includes a plurality of memory devices. The master device transmits a request for a read operation onto the first bus to access data from at least one memory device included in at least one memory subsystem. The first and second memory subsystems each include a transceiver device, a bus, and first and second memory devices. Each transceiver device connects to the first bus. The bus of each memory subsystem connects to each respective transceiver device, wherein each transceiver device is coupled between the first bus and each respective memory subsystem bus. The first and second memory devices in each memory subsystem are coupled respective transceiver devices via respective buses.

Abstract translation: 一种具有主装置和多个存储器子系统的存储器系统，包括耦合到第一总线的第一和第二存储器子系统。 每个存储器子系统包括多个存储器件。 主设备向第一总线发送对读操作的请求，以访问至少一个存储器子系统中包括的至少一个存储设备的数据。 第一和第二存储器子系统各自包括收发器设备，总线以及第一和第二存储器设备。 每个收发器设备连接到第一个总线。 每个存储器子系统的总线连接到每个相应的收发器设备，其中每个收发器设备耦合在第一总线和每个相应的存储器子系统总线之间。 每个存储器子系统中的第一和第二存储器件经由相应的总线耦合到相应的收发器设备。

公开(公告)号：US06182184B2

公开(公告)日：2001-01-30

申请号：US09510213

申请日：2000-02-22

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1300

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling a memory device. The method includes providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be input by the memory device in response to a write request. A first portion of the first amount of data is provided to the memory device synchronously with respect to a first transition of an external clock signal. A second portion of the first amount of data is provided to the memory device synchronously with respect to a second transition of the external clock signal. The method further includes issuing a write request to the memory device, wherein in response to the write request the memory device inputs the first amount of data corresponding to the first block size information.

Abstract translation: 一种控制存储器件的方法。 该方法包括向存储器件提供第一块大小信息，其中第一块大小信息定义响应于写请求由存储器件输入的第一数据量。 相对于外部时钟信号的第一转换，第一数据量的第一部分被同步地提供给存储器件。 相对于外部时钟信号的第二转换，第一数据量的第二部分被同步地提供给存储器件。 该方法还包括向存储器件发出写入请求，其中响应于写入请求，存储器件输入对应于第一块大小信息的第一数据量。

公开(公告)号：US6101152A

公开(公告)日：2000-08-08

申请号：US213243

申请日：1998-12-17

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A synchronous memory device having a plurality of memory cells and a method of operation thereof. The memory device comprising: receiver circuitry to receive a first external clock signal; and output driver circuitry, to output data after a preprogrammed number of clock cycles of the first external clock signal transpire. The data is output synchronously with respect to the first external clock signal. The method of operation comprises: receiving a request for a read operation; sensing data in a portion of the plurality of sense amplifiers in response to the request for a read operation; and outputting the data after a preprogrammed delay time transpires. The method may further include receiving an external clock signal wherein the preprogrammed time delay is representative of a fixed number of clock cycles of the external clock signal. The data is output synchronously with respect to the first external clock signal.

Abstract translation: 一种具有多个存储单元的同步存储器件及其操作方法。 存储器件包括：接收电路，用于接收第一外部时钟信号; 和输出驱动器电路，在第一个外部时钟信号的预编程数量的时钟周期发生后输出数据。 数据相对于第一外部时钟信号同步输出。 所述操作方法包括：接收对读取操作的请求; 响应于对读取操作的请求，感测多个读出放大器的一部分中的数据; 并在预编程的延迟时间发生后输出数据。 该方法还可以包括接收外部时钟信号，其中预编程的时间延迟代表外部时钟信号的固定数量的时钟周期。 数据相对于第一外部时钟信号同步输出。

公开(公告)号：US6070222A

公开(公告)日：2000-05-30

申请号：US263956

申请日：1999-03-08

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: The present invention is directed to a synchronous memory device having a memory cell array divided into a plurality of subarrays, including first and second subarrays each having a plurality of subarray sections. The memory device further includes a device identification register to store an identification code to identify the memory device. A first subarray section in the memory device includes a first internal I/O line to access data from a first memory cell location in the first subarray section and a second internal I/O line to access data from a second memory cell location in the first subarray section. A second subarray section in the memory device includes a first internal I/O line to access data from a third memory cell location in the second subarray section and a second internal I/O line to access data from a fourth memory cell location in the second subarray section. In addition, the memory device includes output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to the read request when the identification information corresponds to the identification code. Multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to a clock edge of a first internal clock signal; and couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal.

Abstract translation: 本发明涉及一种具有被划分成多个子阵列的存储单元阵列的同步存储器件，包括具有多个子阵列部分的第一和第二子阵列。 存储装置还包括用于存储用于识别存储装置的识别码的装置识别寄存器。 存储器件中的第一子阵列部分包括用于从第一子阵列部分中的第一存储器单元位置访问数据的第一内部I / O线和用于从第一内部I / O线中的第一存储器单元位置访问数据的第二内部I / O线 子阵列部分。 存储器装置中的第二子阵列部分包括用于从第二子阵列部分中的第三存储器单元位置访问数据的第一内部I / O线和用于从第二存储单元位置的第二内存I / O行访问数据的第二内部I / O线 子阵列部分。 此外，当识别信息对应于识别码时，存储器件包括输出驱动器电路，包括第一输出驱动器和第二输出驱动器，以响应于读取请求将数据输出到外部总线上。 多路复用器电路将第一子阵列部分的第一内部I / O线耦合到第一输出驱动器的输入，并且响应于时钟将第二子阵列部分的第一内部I / O线耦合到第二输出驱动器的输入 第一内部时钟信号的边沿; 并且将第一子阵列部分的第二内部I / O线耦合到第一输出驱动器的输入端，并响应于时钟沿将第二子阵列部分的第二内部I / O线耦合到第二输出驱动器的输入端 的第二个内部时钟信号。

公开(公告)号：US6035365A

公开(公告)日：2000-03-07

申请号：US200446

申请日：1998-11-27

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device comprises a register to store a value which is representative of a delay time after which the memory device responds to a read request and clock receiver circuitry to receive first and second external clock signals. The memory device also includes an output driver(s) to output data on a bus, in response to a read request and in accordance with the delay time, wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal. The memory device may include a delay locked loop to generate internal clock signal(s) using the external clock signal(s). The output drivers output data on the bus in response to the internal clock signal(s). The memory device may include input receiver circuitry, coupled to the bus, the receive the read request, wherein the read request is sampled from the bus synchronously with respect to the first external clock signal.

Abstract translation: 一种具有至少一个包括多个存储单元的存储器部分的同步存储器件。 该存储器件包括一个寄存器，用于存储表示延迟时间的值，在该延迟时间之后，存储器件响应于读取请求，并且时钟接收器电路接收第一和第二外部时钟信号。 存储器件还包括响应于读取请求并根据延迟时间在总线上输出数据的输出驱动器，其中数据的第一部分相对于第一外部时钟信号被同步输出 并且数据的第二部分相对于第二外部时钟信号被同步地输出。 存储器件可以包括使用外部时钟信号产生内部时钟信号的延迟锁定环路。 输出驱动器响应于内部时钟信号在总线上输出数据。 存储器件可以包括耦合到总线的输入接收器电路，接收读取请求，其中相对于第一外部时钟信号同步从总线对读取请求进行采样。

公开(公告)号：US5953263A

公开(公告)日：1999-09-14

申请号：US196200

申请日：1998-11-20

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1066 ,  G06F13/161 ,  G06F13/1689 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1069 ,  G11C2207/108 ,  Y02B60/1228

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Abstract translation: 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 。 本发明还包括用于主设备和从设备在总线上通信的协议，以及用于每个设备中的寄存器以区分每个设备并允许总线请求被引导到单个或所有设备的协议。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。