公开(公告)号：US11955481B2

公开(公告)日：2024-04-09

申请号：US17992602

申请日：2022-11-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L27/08 ,  H01L21/8228 ,  H01L27/082

CPC classification number: H01L27/0826 ,  H01L21/82285

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

公开(公告)号：US20240105730A1

公开(公告)日：2024-03-28

申请号：US18532984

申请日：2023-12-07

Applicant: STMicroelectronics France ,  STMicroelectronics (Crolles 2) SAS

Inventor： Olivier WEBER ,  Christophe LECOCQ

IPC: H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/092

Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

公开(公告)号：US11901278B2

公开(公告)日：2024-02-13

申请号：US18095629

申请日：2023-01-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Pierre Carrere ,  Francois Guyader

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L31/02

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49894 ,  H01L31/02016

Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.

公开(公告)号：US20240023465A1

公开(公告)日：2024-01-18

申请号：US18186109

申请日：2023-03-17

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bruno REIG ,  Vincent PUYAL ,  Stephane MONFRAY ,  Alain FLEURY ,  Philippe CATHELIN

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/823 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/011

Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.

公开(公告)号：US11875847B2

公开(公告)日：2024-01-16

申请号：US17673550

申请日：2022-02-16

Applicant: Universite D'Aix Marseille ,  Centre National De La Recherche Scientifique ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Jean-Michel Portal ,  Vincenzo Della Marca ,  Jean-Pierre Walder ,  Julien Gasquez ,  Philippe Boivin

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0054 ,  G11C2213/72

Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.

公开(公告)号：US11837678B2

公开(公告)日：2023-12-05

申请号：US17486219

申请日：2021-09-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles Baudot ,  Sebastien Cremer ,  Nathalie Vulliet ,  Denis Pellissier-Tanon

IPC: H01L27/146 ,  H01L31/109 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/105

CPC classification number: H01L31/109 ,  H01L31/028 ,  H01L31/02327 ,  H01L31/105 ,  H01L31/1804

Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.

公开(公告)号：US11830776B2

公开(公告)日：2023-11-28

申请号：US17730691

申请日：2022-04-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L21/82 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/808 ,  H01L29/423 ,  H10B20/00 ,  H01L21/62 ,  H01L21/04

CPC classification number: H01L21/8248 ,  H01L21/046 ,  H01L21/0415 ,  H01L21/62 ,  H01L27/0623 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/66893 ,  H01L29/808 ,  H10B20/40

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

公开(公告)号：US20230369359A1

公开(公告)日：2023-11-16

申请号：US18225298

申请日：2023-07-24

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Francois GUYADER ,  Sara PELLEGRINI ,  Bruce RAE

IPC: H01L27/146 ,  H01L31/107 ,  G01J1/44

CPC classification number: H01L27/1461 ,  H01L31/107 ,  H04N25/70 ,  H01L27/14634 ,  G01J1/44 ,  G01J2001/4466

Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

公开(公告)号：US11811120B2

公开(公告)日：2023-11-07

申请号：US17646964

申请日：2022-01-04

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Victor Fiorese ,  Frederic Gianesello ,  Florian Voineau

IPC: H01P1/161 ,  H01P1/213 ,  H01P5/19 ,  H01Q25/00

CPC classification number: H01P1/161 ,  H01P1/2131 ,  H01P5/19 ,  H01Q25/001

Abstract: An orthomode junction for separating and/or combining orthogonally-polarized radiofrequency wave signals, comprises a body which has a main cavity forming a main waveguide, which has a blind end, and auxiliary cavities forming auxiliary waveguides, which communicate laterally with the main cavity in the vicinity of the blind end thereof, and a deflection insert situated at the blind end of the main cavity and facing the auxiliary cavities, the deflection insert having different shapes on the side of the auxiliary cavities respectively.

公开(公告)号：US20230335515A1

公开(公告)日：2023-10-19

申请号：US18193267

申请日：2023-03-30

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Siddhartha DHAR ,  Frederic GIANESELLO ,  Philippe CATHELIN

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/66 ,  H01L24/32 ,  H01L23/5226 ,  H01L23/5222 ,  H01L24/05 ,  H01L2224/32225 ,  H01L2223/6616 ,  H01L2924/1306

Abstract: The present disclosure is directed to conductive structures that may be utilized in a radio-frequency (RF) switch. The embodiments of the conductive structures of the present disclosure are formed to balance the “on” resistance (Ron) and the “off” capacitance (Coff) such that the Ron·Coff value is optimized such that the conductive structures are relatively efficient as compared to conventional conductive structures within conventional RF switches. For example, the conductive structures include various metallization layers that are stacked on each other and spaced apart in a selected manner to balance the Ron and the Coff as to optimize the Ron·Coff figure of merit as a lower Ron·Coff is preferred.