公开(公告)号：US20240345644A1

公开(公告)日：2024-10-17

申请号：US18638354

申请日：2024-04-17

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics, Inc.

Inventor： Olivier Lemarchand ,  Pierre-Loic Felter ,  Darin K. Winterton ,  Kalyan-Kumar Vadlamudi-Reddy

IPC: G06F1/3231 ,  G01S7/41 ,  G01S13/56

CPC classification number: G06F1/3231 ,  G01S7/415 ,  G01S13/56

Abstract: In accordance with embodiments, methods and systems for utilizing multiple threshold checkers are provided. A range sensor collects measurement data. The range sensor examines the measurement data based on multiple threshold checkers to determine satisfaction of a trigger condition. In response to the satisfaction of the trigger condition, the range sensor provides the measurement data to a host computing device of the range sensor.

公开(公告)号：US12117487B2

公开(公告)日：2024-10-15

申请号：US17654918

申请日：2022-03-15

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Mark Trimmer

IPC: G06F12/14 ,  G01R31/317 ,  G01R31/3185 ,  G11C29/10 ,  G06F1/24 ,  G06F9/448 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C29/52 ,  G11C29/54

CPC classification number: G01R31/31719 ,  G01R31/318588 ,  G06F12/1458 ,  G11C29/10

Abstract: The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.

公开(公告)号：US20240334080A1

公开(公告)日：2024-10-03

申请号：US18616454

申请日：2024-03-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Laurent SIMONY

IPC: H04N25/616 ,  H03F3/45 ,  H04N25/709 ,  H04N25/77

CPC classification number: H04N25/616 ,  H03F3/45475 ,  H04N25/709 ,  H04N25/77 ,  H03F2200/69

Abstract: An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.

公开(公告)号：US12081888B2

公开(公告)日：2024-09-03

申请号：US17660084

申请日：2022-04-21

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Alexandre Mas ,  Abdessamed Mekki ,  Cedric Tubert

IPC: H04N25/75 ,  H03M1/12 ,  H03M1/46 ,  H04N25/625 ,  H04N25/677

CPC classification number: H04N25/75 ,  H03M1/1245 ,  H03M1/46 ,  H04N25/625 ,  H04N25/677

Abstract: The present disclosure relates to a read-out circuit comprising N inputs configured to be connected to N respective outputs of a pixel array of an image sensor, with N being an integer strictly greater than 1; and N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input. In each group, the second inputs of the analog-to-digital converters of the group are connected together, electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and configured to receive a first reference signal that is identical for all the analog-to-digital converters of the group.

公开(公告)号：US12072724B2

公开(公告)日：2024-08-27

申请号：US17453815

申请日：2021-11-05

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Alexandre Pons

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: The present disclosure relates to a device comprising: N low drop-out voltage regulators, N being an integer greater than or equal to 1; a first circuit configured to deliver N set-point voltages to the N regulators which are proportional to the same first current; and a second circuit configured to deliver the first current, wherein the first current is proportional to a reference current modulated based on a sum of the inrush currents of the N regulators.

公开(公告)号：US12057773B2

公开(公告)日：2024-08-06

申请号：US18359548

申请日：2023-07-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau

IPC: H02M3/158

CPC classification number: H02M3/158

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

公开(公告)号：US20240258184A1

公开(公告)日：2024-08-01

申请号：US18630676

申请日：2024-04-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome LOPEZ

IPC: H01L23/31 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52

CPC classification number: H01L23/3114 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

公开(公告)号：US12048099B2

公开(公告)日：2024-07-23

申请号：US17193702

申请日：2021-03-05

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Pierino Calascibetta

IPC: H05K1/18 ,  H01Q1/22 ,  H01Q9/16 ,  H05K1/11

CPC classification number: H05K1/184 ,  H01Q1/22 ,  H01Q9/16 ,  H05K1/115 ,  H05K1/183 ,  H05K2201/10098 ,  H05K2201/10734

Abstract: A base substrate has a thickness between two faces. The base substrate includes at least one hole extending in a thickness of the base substrate perpendicular to one of the two face. At least one dipole of a surface-mount device type is housed in the at least one hole of the base substrate.

公开(公告)号：US20240235555A9

公开(公告)日：2024-07-11

申请号：US18402958

申请日：2024-01-03

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Elias El Haddad ,  Tanguy Tromelin ,  Patrick Bougant ,  Christophe Matheron

IPC: H03K19/173

CPC classification number: H03K19/1737 ,  H03K19/1735

Abstract: A device includes a first AND logic gate comprising a first input, a second input, and an output, a second AND logic gate comprising a first input, a second input, and an output, and a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate. A first selection circuit has first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate. A first D latch includes a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate and a second D latch includes a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate.

公开(公告)号：US12033305B2

公开(公告)日：2024-07-09

申请号：US17112341

申请日：2020-12-04

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Cedric Tubert ,  Jeremie Teyssier ,  Gregory Roffet ,  Stephane Drouard

IPC: G06T5/70 ,  G06T5/20 ,  H04N5/21 ,  H04N25/60

CPC classification number: G06T5/70 ,  G06T5/20 ,  H04N5/21 ,  H04N25/60 ,  G06T2207/20012 ,  G06T2207/20192

Abstract: In an embodiment, a method includes: receiving data signals from a plurality of pixels of an array of pixels; generating a plurality of signal-to-noise ratios by determining signal-to-noise ratios for each respective pixel of the plurality of pixels on the basis of the data signals received from the respective pixel; and filtering the data signals received from each pixel of the plurality of pixels by using an adaptive filter configured on the basis of the plurality of the signal-to-noise ratios to generate filtered data signals.