公开(公告)号：US06754783B2

公开(公告)日：2004-06-22

申请号：US10369301

申请日：2003-02-18

Applicant: Ely K. Tsern ,  Ramprasad Satagopan ,  Richard M. Barth ,  Steven C. Woo

Inventor： Ely K. Tsern ,  Ramprasad Satagopan ,  Richard M. Barth ,  Steven C. Woo

IPC: G06F1200

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  G06F12/0215 ,  G06F2212/1028 ,  G11C11/4074 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.

公开(公告)号：US06721226B2

公开(公告)日：2004-04-13

申请号：US10361109

申请日：2003-02-07

Applicant: Steven C. Woo ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Craig E. Hampel

IPC: G11C700

CPC classification number: G11C5/02

Abstract: Systems and methods for reducing heat flux in memory systems are described. In various embodiments, heat flux reductions are achieved by manipulating the device IDs of individual memory devices that comprise a memory module. Through the various described techniques, the per-face heat flux can be desirably reduced. Further, in some embodiments, reductions in heat flux are achieved by providing control lines that operably connect memory devices on different faces of a memory module.

Abstract translation: 描述了用于减少存储器系统中的热通量的系统和方法。 在各种实施例中，通过操纵包括存储器模块的各个存储器件的器件ID来实现热通量减少。 通过各种描述的技术，可以期望地减少每面热通量。 此外，在一些实施例中，通过提供可操作地连接存储器模块的不同面上的存储器件的控制线来实现热通量的减少。

公开(公告)号：US06552948B2

公开(公告)日：2003-04-22

申请号：US09989953

申请日：2001-11-21

Applicant: Steven C. Woo ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Craig E. Hampel

IPC: G11C700

CPC classification number: G11C5/02

Abstract: Systems and methods for reducing heat flux in memory systems are described. In various embodiments, heat flux reductions are achieved by manipulating the device IDs of individual memory devices that comprise a memory module. Through the various described techniques, the per-face heat flux can be desirably reduced. Further, in some embodiments, reductions in heat flux are achieved by providing control lines that operably connect memory devices on different faces of a memory module.

公开(公告)号：US09263103B2

公开(公告)日：2016-02-16

申请号：US12049928

申请日：2008-03-17

Applicant: Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00 ,  G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。 在该系统的变型中，存储器芯片上的相位检测器被配置为从存储器控制器接收包括时钟信号，标记信号和数据选通信号的信号，其中标记信号包括标记特定时钟的脉冲 在时钟信号周期。 在该变型中，相位检测器被配置为使用标记信号来在时钟信号中画出特定时钟周期，并且使用数据选通信号来捕获窗口化的时钟信号，从而产生返回到 内存控制器便于校准时序关系。

公开(公告)号：US20150255144A1

公开(公告)日：2015-09-10

申请号：US14698755

申请日：2015-04-28

Applicant: Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。

公开(公告)号：US08935489B2

公开(公告)日：2015-01-13

申请号：US13500067

申请日：2010-11-10

Applicant: Steven C. Woo ,  Trung A. Diep ,  Michael T. Ching

Inventor： Steven C. Woo ,  Trung A. Diep ,  Michael T. Ching

IPC: G06F12/00 ,  G06F13/16 ,  G06F9/52

CPC classification number: G06F13/1652 ,  G06F9/5016 ,  G06F9/52

Abstract: The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.

Abstract translation: 所公开的实施例涉及用于处理从多个处理器核心接收的存储器参考的系统。 在操作期间，系统监视存储器引用以确定来自不同处理器核的存储器引用是否因存储器引用被存储器系统处理而彼此干扰。 如果来自不同处理器核心的存储器引用彼此干扰，则系统对处理器内核之间的存储器引用进行时间复用，从而在存储器引用之前由存储器系统处理来自给定处理器内核的连续存储器引用块 处理其他处理器内核。

公开(公告)号：US08665642B2

公开(公告)日：2014-03-04

申请号：US13140345

申请日：2009-10-08

Applicant: Bohuslav Rychlik ,  John Eric Linstadt ,  Brent Steven Haukness ,  Steven C. Woo

Inventor： Bohuslav Rychlik ,  John Eric Linstadt ,  Brent Steven Haukness ,  Steven C. Woo

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628

Abstract: A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits.

Abstract translation: 一种操作存储器件的方法包括接收要存储在器件中的多级单元中的第一组和第二组位。 从用于存储多级单元中的第一和第二位组的多个多级编码中选择多级编码。 每个多级编码包括用于相应多级单元的至少四个编码电平。 相应的多级编码具有与根据相应的多级编码将第一和第二组位编程到多级单元中相关联的成本。 基于相应编码的相应成本来选择多级编码。 第一和第二组位根据所选择的多级编码进行编码，以产生用于存储在设备中的编码数据，使得相应的多级单元存储来自第一和第二组位的相应位。

公开(公告)号：US20130194881A1

公开(公告)日：2013-08-01

申请号：US13878419

申请日：2011-11-07

Applicant: Steven C. Woo ,  Amir Amirkhany ,  Catherine Chen ,  David Secker ,  Jie Shen

Inventor： Steven C. Woo ,  Amir Amirkhany ,  Catherine Chen ,  David Secker ,  Jie Shen

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F13/1694

Abstract: One or more pins may be modally assigned to either the command/address (C/A) or data (DQ) blocks of a uniform-package, multi-modal PHY (physical signaling interface) of a memory controller, thus enabling those pins to be used as C/A pins when the PHY is connected to some memory types, and as DQ pins when the PHY is connected to other memory types.

Abstract translation: 一个或多个引脚可以被模式地分配给存储器控制器的均匀封装，多模态PHY（物理信令接口）的命令/地址（C / A）或数据（DQ）块，从而使得这些引脚 当PHY连接到某些存储器类型时，用作C / A引脚，当PHY连接到其他存储器类型时用作引脚。

公开(公告)号：US08473681B2

公开(公告)日：2013-06-25

申请号：US13143993

申请日：2010-02-02

Applicant: Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohuslav Rychlik

Inventor： Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohuslav Rychlik

IPC: G06F13/00

CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815

Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

Abstract translation: 缓存相干协议在共享内存空间的多个处理器（或处理器核心）之间分配原子操作。 当包括修改存储在共享存储器空间中的数据的指令的原子操作被引导到不具有与数据相关联的地址的控制的第一处理器时，第一处理器发送包括指令的请求 修改数据到第二个处理器。 然后，已经具有对地址的控制的第二处理器修改数据。 此外，第一处理器可以立即进行另一个指令，而不是等待地址变得可用。

公开(公告)号：US08332556B2

公开(公告)日：2012-12-11

申请号：US13349210

申请日：2012-01-12

Applicant: Steven C. Woo ,  Scott C. Best

Inventor： Steven C. Woo ,  Scott C. Best

IPC: G06F13/00

CPC classification number: E04B2/58 ,  E04B1/24 ,  E04C2/423 ,  G06F13/4243

Abstract: A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract translation: 存储器总线，其具有耦合到存储器控制器的第一总线段，存储器控制器包括控制逻辑和第一存储器件，耦合到第二存储器件的第二总线段以及第一总线段和第二总线段之间的开关。 控制逻辑将控制信息输出到开关以选择性地分离第一总线段和第二总线段以实现存储器总线的长度的改变，以使得能够以第一数据速率相对于第一存储器件的数据传输。 另外，控制逻辑可以将控制信息输出到开关以选择性地耦合第一总线段和第二总线段以增加存储器总线的长度，以使得能够以第二数据速率相对于第二存储器设备进行数据传输， 比第一个数据速率慢。