公开(公告)号：US5587332A

公开(公告)日：1996-12-24

申请号：US938727

申请日：1992-09-01

申请人： Kuang-Yeh Chang ,  Subhash R. Nariani ,  William J. Boardman

发明人： Kuang-Yeh Chang ,  Subhash R. Nariani ,  William J. Boardman

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： The present invention relates to a flash EEPROM cell using polysilicon-to-polysilicon hot electron emission to erase the memory contents of the cell. Exemplary embodiments include a side gate, a control gate, a floating gate and source and drain regions. Appropriate biasing of these gates and source and drain regions controls the electron population of the floating gate. The memory cells may be of either the double polysilicon or triple polysilicon variety. Peripheral transistors are formed from a last formed polysilicon layer to avoid degrading the peripheral transistors.

摘要翻译： 本发明涉及使用多晶硅 - 多晶硅热电子发射来擦除单元的存储器内容的快闪EEPROM单元。 示例性实施例包括侧栅极，控制栅极，浮置栅极和源极和漏极区域。 这些栅极和源极和漏极区域的适当偏置控制浮栅的电子群。 存储单元可以是双重多晶硅或三重多晶硅品种。 外围晶体管由最后形成的多晶硅层形成，以避免外围晶体管的劣化。

公开(公告)号：US5290734A

公开(公告)日：1994-03-01

申请号：US736162

申请日：1991-07-26

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L21/283 ,  H01L21/311

CPC分类号： H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, a conductive protective material, such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distributions for the anti-fuse structure and help prevent anti-fuse failure.

摘要翻译： 一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的衬底上的氧化物层，设置在开口内并接触衬底的非晶硅材料，设置在非晶态上的导电保护材料，例如钛钨 硅材料和衬在保护材料内形成的凹部的壁上的氧化物间隔物。 保护材料和间隔物为反熔丝结构提供更严格的编程电压分布，并有助于防止反熔丝故障。

公开(公告)号：US5218511A

公开(公告)日：1993-06-08

申请号：US902197

申请日：1992-06-22

申请人： Subhash R. Nariani

发明人： Subhash R. Nariani

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822

CPC分类号： H01L28/60

摘要： A method produces a capacitor. On a substrate, a polysilicon layer is formed over an insulating region. A first metal-silicide layer is formed on top of the polysilicon layer. A dielectric layer is formed on top of the first metal-silicide layer. A second metal-silicide layer is formed on top of the dielectric layer. The second metal-silicide layer and the dielectric layer are etched to form a top electrode and dielectric region. The first metal-silicide layer and the polysilicon layer are etched to form a bottom electrode.

摘要翻译： 一种方法产生电容器。 在衬底上，在绝缘区域上形成多晶硅层。 第一金属硅化物层形成在多晶硅层的顶部上。 介电层形成在第一金属硅化物层的顶部。 第二金属硅化物层形成在电介质层的顶部。 蚀刻第二金属硅化物层和电介质层以形成顶部电极和电介质区域。 第一金属硅化物层和多晶硅层被蚀刻以形成底部电极。

公开(公告)号：US5198381A

公开(公告)日：1993-03-30

申请号：US758554

申请日：1991-09-12

申请人： Kuang-Yeh Chang ,  Subhash R. Nariani

发明人： Kuang-Yeh Chang ,  Subhash R. Nariani

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28273 ,  Y10S438/981

摘要： The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

摘要翻译： 本发明涉及一种用于制造具有改进的隧道面积的半导体存储器件，特别是E2PROM的半导体存储器件和方法，其中电子行进到浮栅。 隧道区域的特点是在E2PROM的使用寿命期间可以实现相对较多的编程和擦除循环。 隧道区域包括通过两个植入阶段制造的隧道门。 因为这两个阶段是彼此分开的，因此可以独立地优化每个植入阶段以改善隧道区域的性质。 此外，用于限定植入区域的窗口容易制造并且被设计成有利于植入区域的形成。 定义窗口的方法有助于轻松扩展用于推进世代技术的过程。

公开(公告)号：US5763937A

公开(公告)日：1998-06-09

申请号：US277090

申请日：1994-07-19

申请人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

发明人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

IPC分类号： H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L27/115 ,  H01L29/78 ,  H01L23/58

CPC分类号： H01L29/6659 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/314 ,  H01L21/31612 ,  H01L21/76801 ,  H01L23/291 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002

摘要： The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

摘要翻译： 本发明涉及用于制造具有多层金属化的MOS器件的MOS器件和方法。 根据优选实施例，内部钝化用于抑制来自内部源的器件劣化。 用于制造这种器件的优选器件和方法包括形成富含硅的一个或多个氧化物层以提供这种内部钝化并改善热载流子寿命。 用于制造具有多层金属化的MOS器件的优选方法包括改变PECVD氧化物膜的组成，并且在一些实施例中改变这种氧化物的位置和厚度。 在示例性优选实施例中，通过将组合物改变为富含氧化物的氧化物来修饰PECVD氧化物层。

公开(公告)号：US5548224A

公开(公告)日：1996-08-20

申请号：US376590

申请日：1995-01-20

申请人： Calvin T. Gabriel ,  Subhash R. Nariani

发明人： Calvin T. Gabriel ,  Subhash R. Nariani

IPC分类号： G01R31/28 ,  H01L21/66 ,  G01R31/26

CPC分类号： G01R31/2856 ,  G01R31/2831 ,  H01L22/12 ,  H01L22/14

摘要： An IC wafer containing thin oxide is fabricated with at least one pair of antenna structures having identical antenna ratio A.sub.R but different antenna plate areas. Each antenna structure includes connected-together conductive plate regions, one plate formed over thick field oxide and the other plate formed over thin oxide on the IC. Because weak oxide defects occur somewhat uniformly throughout the thin oxide, a larger antenna structure will overlie more weak oxide defects than will a smaller antenna structure. If wafer test leakage current across the larger antenna structure exceeds leakage current across the smaller antenna structure, weak oxide is indicated because the defect is area dependent. By contrast, charge-induced damage is substantially independent of the area of the antenna plates. Because the A.sub.R ratios are constant, charge density is constant in the antenna structure portions overlying the thin oxide. If test leakage current on the wafer is substantially the same for each antenna structure, charge-damaged oxide is indicated because the damage is not area dependent. If desired, test MOS devices may be fabricated whose gates are the plates formed over the thin oxide. Defects in the thin (gate) oxide may be identified by examining the characteristics of the test MOS devices.

摘要翻译： 制造含有薄氧化物的IC晶片，其具有至少一对天线结构，天线结构具有相同的天线比AR但不同的天线板面积。 每个天线结构包括连接在一起的导电板区域，一个板形成在厚场氧化物上，另一个板形成在IC上的薄氧化物上。 由于弱的氧化物缺陷在整个薄氧化物中有些均匀地发生，所以与较小的天线结构相比，较大的天线结构将覆盖更多的弱氧化物缺陷。 如果跨越较大天线结构的晶片测试漏电流超过较小天线结构的漏电流，则表示弱氧化物，因为缺陷是面积依赖的。 相反，电荷引起的损伤基本上与天线板的面积无关。 由于AR比率恒定，覆盖薄氧化物的天线结构部分的电荷密度是恒定的。 如果晶片上的测试泄漏电流对于每个天线结构基本相同，则表示电荷损坏的氧化物，因为损伤不是区域依赖性的。 如果需要，可以制造测试MOS器件，其栅极是在薄氧化物上形成的板。 可以通过检查测试MOS器件的特性来识别薄（栅极）氧化物中的缺陷。

公开(公告)号：US5493146A

公开(公告)日：1996-02-20

申请号：US275187

申请日：1994-07-14

申请人： Dipankar Pramanik ,  Subhash R. Nariani

发明人： Dipankar Pramanik ,  Subhash R. Nariani

IPC分类号： H01L23/525 ,  H01L29/00 ,  H01L23/48 ,  H01L29/04

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.

公开(公告)号：US5371393A

公开(公告)日：1994-12-06

申请号：US221463

申请日：1994-04-01

申请人： Kuang-Yeh Chang ,  Subhash R. Nariani

发明人： Kuang-Yeh Chang ,  Subhash R. Nariani

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L21/28273 ,  Y10S438/981

摘要： The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

摘要翻译： 本发明涉及一种用于制造具有改进的隧道面积的半导体存储器件，特别是E2PROM的半导体存储器件和方法，其中电子行进到浮栅。 隧道区域的特点是在E2PROM的使用寿命期间可以实现相对较多的编程和擦除循环。 隧道区域包括通过两个植入阶段制造的隧道门。 因为这两个阶段是彼此分开的，因此可以独立地优化每个植入阶段以改善隧道区域的性质。 此外，用于限定植入区域的窗口容易制造并且被设计成有利于植入区域的形成。 定义窗口的方法有助于轻松扩展用于推进世代技术的过程。

公开(公告)号：US5120679A

公开(公告)日：1992-06-09

申请号：US710220

申请日：1991-06-04

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/82 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, and oxide spacers lining the walls of a recess formed within the amorphous silicon. The spacers prevent failures of the anti-fuse structures by covering cusps formed in the amorphous silicon material. The method of the present invention forms the above-described anti-fuse structure and further solves the problem of removing unwanted spacer material from areas outside of the anti-fuse structure locations.

摘要翻译： 一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的基底上的氧化物层，设置在开口内并接触基底的非晶硅材料以及衬在非晶硅内形成的凹陷壁的氧化物间隔物 。 间隔物通过覆盖形成在非晶硅材料中的尖头来防止抗熔丝结构的故障。 本发明的方法形成上述反熔丝结构，并且进一步解决了从抗熔丝结构位置之外的区域去除不想要的隔离材料的问题。

公开(公告)号：US5057897A

公开(公告)日：1991-10-15

申请号：US476089

申请日：1990-03-05

申请人： Subhash R. Nariani ,  Dipankar Pramanik

发明人： Subhash R. Nariani ,  Dipankar Pramanik

IPC分类号： H01L21/314 ,  H01L23/29 ,  H01L23/532 ,  H01L27/115

CPC分类号： H01L23/298 ,  H01L21/314 ,  H01L23/291 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002

摘要： Parasitic leakage is minimized in a MOS structure. An integrated circuit wafer comprises conventional MOS elements as applied through a first level metallization. An intermetal dielectric includes three layers, an intermediate organic glass layer used for planarization and upper and lower oxide layers. A second metallization is applied over the dielectric. Passivation includes a lower oxide passivation and an upper nitride passivation. Hydrogen from the nitride passivation migrates into the organic glass and forms positive charges that induce the parasitic leakage. The lower oxide layer in the intermetal dielectric is silicon-enriched to provide dangling bonds which neutralize this charge formation and thus minimize the parasitic leakage.

摘要翻译： 在MOS结构中寄生泄漏最小化。 集成电路晶片包括通过第一级金属化施加的常规MOS元件。 金属间电介质包括三层，用于平坦化的中间有机玻璃层和上部和下部氧化物层。 在电介质上施加第二金属化。 钝化包括较低的氧化物钝化和上部氮化物钝化。 来自氮化物钝化的氢迁移到有机玻璃中并形成诱发寄生泄漏的正电荷。 金属间电介质中的低氧化物层是富含硅的，以提供悬挂键，其中和这种电荷形成，从而最小化寄生泄漏。