公开(公告)号：US20070075381A1

公开(公告)日：2007-04-05

申请号：US11241878

申请日：2005-09-30

Applicant: Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

Inventor： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

IPC: H01L29/76

CPC classification number: H01L27/115 ,  H01L27/11565 ,  H01L27/11568

Abstract: The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

Abstract translation: 位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。 横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。 在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。 在阻塞区域之间，字线正常布置在位线上。

公开(公告)号：US20070057318A1

公开(公告)日：2007-03-15

申请号：US11228036

申请日：2005-09-15

Applicant: Lars Bach ,  Dominik Olligs ,  Torsten Mueller ,  Veronika Polei

Inventor： Lars Bach ,  Dominik Olligs ,  Torsten Mueller ,  Veronika Polei

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/7923 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42352

Abstract: A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or by forming sidewall spacers and removing portions of the memory layer that are not covered by the spacers. A gate electrode is applied into the recess, and source/drain regions are formed by an implantation of doping atoms adjacent to the sidewalls of the recess and the remaining portions of the memory layer. The memory layer can especially be a dielectric material suitable for charge-trapping.

Abstract translation: 半导体衬底设置有凹部。 存储层或存储器层序列被施加到凹槽的侧壁和底部。 存储层通过将存储层减小到侧壁间隔物或通过形成侧壁间隔物和去除未被间隔物覆盖的存储层的部分而在凹槽的相对侧壁处形成两个分开的部分。 栅电极被施加到凹槽中，并且通过注入与凹槽的侧壁和存储层的其余部分相邻的掺杂原子来形成源/漏区。 存储层可以特别地是适用于电荷俘获的电介质材料。

公开(公告)号：US09099508B2

公开(公告)日：2015-08-04

申请号：US13256382

申请日：2010-04-09

Applicant: Andreas Hertgens ,  Torsten Mueller ,  Paul Waltner

Inventor： Andreas Hertgens ,  Torsten Mueller ,  Paul Waltner

IPC: H01L21/68 ,  H01L21/67 ,  H01L21/677 ,  H01L21/687

CPC classification number: H01L21/67259 ,  H01L21/67265 ,  H01L21/67778 ,  H01L21/681 ,  H01L21/68707

Abstract: The invention relates to a method for automatic measurement and for teaching-in of location positions of objects (11) within a substrate processing system (20, 26) in which a sensor carrier (1) is moved by means of a robot end effector (24). Sensor units (2, 3, 4, 5a, 5b) of the sensor carrier (1) are moved along straight movement lines (B1, B2, B3) across the edges (10a, 10b) of the object (11), wherein each of the sensor units (2, 3, 4, 5a, 5b) output at least one sensor signal which changes its value upon detection of an edge (10a, 10b). From the positions of the signal changes along the respective straight movement lines (B1, B2, B3), the location position of the object (11) is determined. Furthermore, the invention relates to a substrate like movable, wireless sensor carrier for carrying out the method according to the invention, with a carrier plate (1a), at least one first sensor unit (4, 5a, 5b) which is mounted on the carrier plate (1a) and which is arranged to detect a first object edge (10a) and a second object edge (10b) of the object (11) during a movement of the sensor carrier (1) on a straight movement line (B1) perpendicular to an object surface (13), and at least one second sensor unit (2, 3) which is mounted on the carrier plate (Ia) and which is arranged to detect at least a first object edge (10b) of the object (11) during a movement of the sensor carrier (1) on a straight movement line (B2) parallel to the object surface (13).

Abstract translation: 本发明涉及一种用于自动测量和用于在基板处理系统（20,26）内的物体（11）的位置的教导的方法，其中传感器载体（1）借助于机器人末端执行器 24）。 传感器载体（1）的传感器单元（2,3,4,5a，5b）跨越物体（11）的边缘（10a，10b）沿直线移动线（B1，B2，B3）移动，其中每个 传感器单元（2,3,4,5a，5b）输出至少一个在检测到边缘（10a，10b）时改变其值的传感器信号。 根据沿各个直线运动线（B1，B2，B3）的信号变化的位置，确定物体（11）的位置位置。 此外，本发明涉及一种用于执行根据本发明的方法的可移动的无线传感器载体，其具有载体板（1a），至少一个第一传感器单元（4,5a，5b），其安装在 载体板（1a），其被布置成在传感器载体（1）在直线移动线（B1）移动期间检测物体（11）的第一物体边缘（10a）和第二物体边缘（10b） 垂直于物体表面（13）的至少一个第二传感器单元（2,3），以及安装在载体板（1a）上并被布置成检测物体的至少第一物体边缘（10b）的至少一个第二传感器单元（2,3） （1）在平行于物体表面（13）的直线移动线（B2）上运动期间。

公开(公告)号：US08845487B2

公开(公告)日：2014-09-30

申请号：US13228761

申请日：2011-09-09

Applicant: Torsten Mueller

Inventor： Torsten Mueller

IPC: F16H61/662 ,  F16H7/12 ,  F02B67/06 ,  F16H7/08

CPC classification number: F02B67/06 ,  F16H7/1263 ,  F16H2007/0802 ,  F16H2007/0823 ,  F16H2007/0885 ,  Y10T477/6237

Abstract: A tensioning device is provided for a ribbed V-belt of a motor vehicle with at least one tensioning pulley that is directly and functionally connected to the ribbed V-belt and with a controller designed for varying the position and/or configuration of the tensioning pulley in dependence on the instantaneous operating state of at least one belt pulley on a driven side and/or a driving side that is connected to the ribbed V-belt in order to operationally adapt the tension of the ribbed V-belt.

Abstract translation: 提供了一种用于机动车辆的带肋V形带的张紧装置，其具有直接和功能地连接到带肋V形带的至少一个张紧轮，并具有设计用于改变张紧轮的位置和/或构造的控制器 这取决于驱动侧和/或连接到带肋V形带的驱动侧的至少一个皮带轮的瞬时操作状态，以便可操作地适应带肋V形带的张力。

公开(公告)号：US08589047B2

公开(公告)日：2013-11-19

申请号：US13197916

申请日：2011-08-04

Applicant: Torsten Mueller

Inventor： Torsten Mueller

IPC: F02D28/00

CPC classification number: F02D41/123 ,  B60W10/06 ,  B60W10/08 ,  B60W10/188 ,  B60W30/18127 ,  B60W2540/10 ,  B60W2540/12 ,  B60W2710/0605 ,  B60W2710/083 ,  F02D41/0002 ,  F02D2200/602 ,  F02D2250/24 ,  F02D2250/41 ,  Y02T10/42

Abstract: A method is provided for operating a combustion engine of a motor vehicle during a deceleration of the combustion engine. The method includes, but is not limited to determining a degree of depression of an accelerator pedal of the motor vehicle takes place, determining of a degree of depression of a brake pedal of the motor vehicle takes place. Furthermore, an adjusting of a throttle valve arranged in an intake tract of the combustion engine as a function of the determined degree of depression of the accelerator pedal and as a function of the determined degree of depression of the brake pedal takes place. The throttle valve is adjusted into an at least partially opened position in the event that the determined degree of depression of the brake pedal undershoots a first predetermined threshold value and the throttle valve is adjusted into a closed position in the event that the determined degree of depression of the brake pedal exceeds a second predetermined threshold value.

Abstract translation: 提供一种用于在内燃机的减速期间操作机动车辆的内燃机的方法。 该方法包括但不限于确定发生机动车辆的加速器踏板的程度，确定机动车辆的制动踏板的下压程度。 此外，发生作为确定的加速器踏板的压下程度的函数调节布置在内燃机的进气道中的节流阀，并且作为确定的制动踏板的压下程度的函数。 在确定的制动踏板的下压程度下冲第一预定阈值的情况下，将节流阀调节到至少部分打开的位置，并且在确定的抑制程度的情况下将节流阀调节到关闭位置 的制动踏板超过第二预定阈值。

公开(公告)号：US20110120091A1

公开(公告)日：2011-05-26

申请号：US12862469

申请日：2010-08-24

Applicant: Alexander LEU ,  Torsten MUELLER ,  Markus WESSLAU

Inventor： Alexander LEU ,  Torsten MUELLER ,  Markus WESSLAU

IPC: F01N11/00

CPC classification number: F01N11/002 ,  F01N2550/02 ,  F02D41/0005 ,  F02D41/025 ,  F02D41/0255 ,  F02D41/062 ,  F02D41/1446 ,  F02D41/405 ,  F02D2200/0804 ,  Y02T10/26 ,  Y02T10/47

Abstract: A method is provided for monitoring the light-off temperature of a diesel oxidation catalyst of a combustion engine. The method includes, but is not limited to measuring the temperature of the exhaust gas upstream and downstream of the diesel oxidation catalyst during a post injection phase or after injection phase of the combustion engine, determining whether a catalyst light-off occurred by using the temperature data of the exhaust gas, calculating the surface temperature of the diesel oxidation catalyst by using the measured temperature data of the exhaust gas, and defining the calculated temperature as light-off temperature of the diesel oxidation catalyst in the case that a catalyst light-off is determined. By means of the method, it is possible to determine the actual light-off temperature of the diesel oxidation catalyst for instance after each engine start by means of calculating the surface temperature of the diesel oxidation catalyst. Since the light-off temperature is not considered as a constant but as a changing variable, the aging of the diesel oxidation catalyst is sufficiently considered. Thus, it is provided a means for monitoring the light-off temperature of a diesel oxidation catalyst considering an aging of the diesel oxidation catalyst.

Abstract translation: 提供了一种监测内燃机柴油机氧化催化剂的点火温度的方法。 该方法包括但不限于在内燃机的后喷射阶段或喷射阶段之后测量柴油机氧化催化剂的上游和下游的废气的温度，确定是否通过使用温度来发生催化剂点火 废气的数据，通过使用测定的废气温度数据计算柴油机氧化催化剂的表面温度，并且在催化剂熄灭的情况下将所计算的温度定义为柴油机氧化催化剂的关闭温度 决心，决意，决定。 通过该方法，可以通过计算柴油机氧化催化剂的表面温度来确定例如在每个发动机启动之后的柴油氧化催化剂的实际点火温度。 由于关闭温度不被认为是常数，而是作为变化的变量，充分考虑了柴油机氧化催化剂的老化。 因此，考虑到柴油机氧化催化剂的老化，提供了用于监测柴油机氧化催化剂的起燃温度的手段。

公开(公告)号：US07935608B2

公开(公告)日：2011-05-03

申请号：US12131794

申请日：2008-06-02

Applicant: Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

Inventor： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

IPC: H01L21/76

CPC classification number: H01L27/1203 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/11517 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

Abstract translation: 提供了一种用于制造包括至少一个存储单元的集成电路的方法。 该方法包括提供具有第一和第二侧面以及多个平行沟槽的衬底，使得在相邻沟槽之间形成分隔壁，用绝缘化合物填充沟槽，从而提供第一和第二侧面的第一绝缘层 分隔壁的上表面，其中第一侧布置在基板的第一侧上，提供具有第一和第二侧的第一导电层，其中第一侧布置在绝缘层的第二侧上，其中导电层突出 从基板表面提供具有第一和第二侧面的第二导电层，其中第一侧位于第一导电层的第二侧上，并通过各向异性蚀刻装置去除第二导电层的部分。

公开(公告)号：US20090294825A1

公开(公告)日：2009-12-03

申请号：US12131794

申请日：2008-06-02

Applicant: Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

Inventor： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/1203 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/11517 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

Abstract translation: 提供了一种用于制造包括至少一个存储单元的集成电路的方法。 该方法包括提供具有第一和第二侧面以及多个平行沟槽的衬底，使得在相邻沟槽之间形成分隔壁，用绝缘化合物填充沟槽，从而提供第一和第二侧面的第一绝缘层 分隔壁的上表面，其中第一侧布置在基板的第一侧上，提供具有第一和第二侧的第一导电层，其中第一侧布置在绝缘层的第二侧上，其中导电层突出 从基板表面提供具有第一和第二侧面的第二导电层，其中第一侧位于第一导电层的第二侧上，并通过各向异性蚀刻装置去除第二导电层的部分。

公开(公告)号：US20070178684A1

公开(公告)日：2007-08-02

申请号：US11344961

申请日：2006-01-31

Applicant: Torsten Mueller ,  Josef Willer ,  Stephanie Iacono

Inventor： Torsten Mueller ,  Josef Willer ,  Stephanie Iacono

IPC: H01L21/44

CPC classification number: H01L27/0203 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/222

Abstract: A periodic pattern of conductor tracks with broader interspaces is produced by the application of a totally periodic pattern and subsequent removal of individual conductor tracks. An alternative method comprises the formation of a completely periodic hardmask, from which individual parts are removed. The modified hardmask is then used to etch a periodic pattern of conductor tracks with intermediate broader spaces.

Abstract translation: 具有较宽空间的导体轨迹的周期性图案通过施加全周期图案并随后移除各个导体轨迹来产生。 一种替代方法包括形成完全周期性的硬掩模，从其中去除各个部件。 然后使用改进的硬掩模来蚀刻具有中间较宽空间的导体轨迹的周期性图案。

公开(公告)号：US20070082446A1

公开(公告)日：2007-04-12

申请号：US11246908

申请日：2005-10-07

Applicant: Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

Inventor： Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L27/115 ,  H01L21/76897 ,  H01L27/11568

Abstract: A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.

Abstract translation: 提供了用于制造堆叠的非易失性存储单元的方法。 提供具有形成埋入位线的多个扩散区域的半导体晶片。 电荷捕获层和导电层沉积在半导体晶片的表面上。 在导电层的顶部使用掩模层，形成绝缘层的接触孔。 蚀刻停止层沉积在半导体晶片的表面上。 在蚀刻停止层上方，沉积介电层并图案化以形成接触孔。 随后，接触孔通过蚀刻停止层和绝缘层扩大到埋入位线。