公开(公告)号：US07422020B2

公开(公告)日：2008-09-09

申请号：US11479519

申请日：2006-06-30

Applicant: Vijayakumar Ramachandrarao ,  Grant Kloster

Inventor： Vijayakumar Ramachandrarao ,  Grant Kloster

IPC: B08B6/00 ,  H01L21/302

CPC classification number: C03C17/007 ,  C03C2217/425

Abstract: A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer.

Abstract translation: 在基板上形成多孔介电层。 铝通过使用铝气体前体的图案方法结合在多孔介电层中。 结合的铝改善了多孔介电层的机械性能。

公开(公告)号：US07303648B2

公开(公告)日：2007-12-04

申请号：US10854541

申请日：2004-05-25

Applicant: Hyun-Mog Park ,  Vijayakumar Ramachandrarao

Inventor： Hyun-Mog Park ,  Vijayakumar Ramachandrarao

IPC: H01L21/3065

CPC classification number: H01L21/31116 ,  H01L21/76804 ,  Y10S438/978

Abstract: Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.

Abstract translation: 在一个实施方案中，与集成电路器件中的蚀刻通孔相关的系统和技术包括：提供介电材料和导电材料，去除电介质材料的第一部分以在电介质材料中形成孔，执行去除 电介质材料的第二部分以形成在导电材料上接触的通孔，并且横向膨胀通孔的底部尺寸，而不会明显增加通孔的深度。 该技术还可以包括：提供具有介电材料和导电材料的基底，没有相关联的蚀刻停止层，以高蚀刻速率去除第一部分，控制离子轰击和等离子体化学以形成通孔的倾斜底部， 并执行强烈的离子轰击等离子体蚀刻，横向扩展通孔底部。

公开(公告)号：US20060281329A1

公开(公告)日：2006-12-14

申请号：US11150498

申请日：2005-06-10

Applicant: Vijayakumar RamachandraRao ,  Boyan Boyanov ,  Grant Kloster ,  Hyun-Mog Park

Inventor： Vijayakumar RamachandraRao ,  Boyan Boyanov ,  Grant Kloster ,  Hyun-Mog Park

IPC: H01L21/469 ,  H01L21/31

CPC classification number: H01L21/3105 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/02362 ,  H01L21/31058 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76831

Abstract: A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectric layer with a silazane to form a monolayer of silane molecules on the surface, and applying a second plasma to the surface of the dielectric layer to induce a polymerization of at least a portion of the silane molecules. The polymerized silane molecules form a cross-linked matrix that builds over a substantial portion of the surface of the dielectric layer and seals at least some of the exposed pores.

Abstract translation: 一种用于在衬底顶部密封多孔电介质层的方法，其中所述介电层被图案化以形成至少沟槽和至少通孔，包括将第一等离子体施加到所述电介质层的表面以使所述表面硅烷醇化，处理所述表面 的介电层与硅氮烷反应以在表面上形成单层的硅烷分子，并将第二等离子体施加到电介质层的表面以引起至少一部分硅烷分子的聚合。 聚合的硅烷分子形成交联的基质，其形成在电介质层的表面的大部分上并且密封至少一些暴露的孔。

公开(公告)号：US20060138618A1

公开(公告)日：2006-06-29

申请号：US11359002

申请日：2006-02-21

Applicant: Vijayakumar RamachandraRao ,  Shriram Ramanathan

Inventor： Vijayakumar RamachandraRao ,  Shriram Ramanathan

IPC: H01L23/495

CPC classification number: H01L24/11 ,  H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08148 ,  H01L2224/13147 ,  H01L2224/16148 ,  H01L2224/81013 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A method for wafer stacking employing substantially uniform copper structures is described herein.

Abstract translation: 本文描述了使用基本均匀的铜结构的晶片堆叠方法。

公开(公告)号：US20050079685A1

公开(公告)日：2005-04-14

申请号：US10683202

申请日：2003-10-09

Applicant: Shriram Ramanathan ,  Grant Kloster ,  Patrick Morrow ,  Vijayakumar RamachandraRao ,  Scott List

Inventor： Shriram Ramanathan ,  Grant Kloster ,  Patrick Morrow ,  Vijayakumar RamachandraRao ,  Scott List

IPC: H01L21/46 ,  H01L23/485 ,  H01L25/065

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14

Abstract: The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.

Abstract translation: 本发明提供了具有降低的故障的堆叠晶片结构。 在一个实施例中，存在沉积在导体的暴露表面上的阻挡层，其延伸跨越第一和第二器件结构之间的距离。 阻挡层可以防止导体材料的扩散和电迁移，这可能降低层叠晶片结构中的短路和空隙的发生。

公开(公告)号：US20060292856A1

公开(公告)日：2006-12-28

申请号：US11169367

申请日：2005-06-28

Applicant: Hyun-Mog Park ,  Boyan Boyanov ,  Grant Kloster ,  Vijayakumar RamachandraRao

Inventor： Hyun-Mog Park ,  Boyan Boyanov ,  Grant Kloster ,  Vijayakumar RamachandraRao

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/02063 ,  H01L21/3105 ,  H01L21/31138 ,  H01L21/76814 ,  H01L21/76844

Abstract: A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other embodiments are described and claimed.

Abstract translation: 图案化多孔电介质材料的方法，其包括用于处理多孔介电材料的灰过程。 经处理的多孔介电材料允许形成基本上连续的阻挡层，其可阻止例如导电材料扩散到电介质材料中。 描述和要求保护其他实施例。

公开(公告)号：US20060108067A1

公开(公告)日：2006-05-25

申请号：US11327930

申请日：2006-01-09

Applicant: Subramanyam Iyer ,  Justin Brask ,  Vijayakumar Ramachandrarao

Inventor： Subramanyam Iyer ,  Justin Brask ,  Vijayakumar Ramachandrarao

IPC: C23F1/00

CPC classification number: H01L22/26 ,  H01L21/02052 ,  H01L21/306 ,  H01L21/31116 ,  H01L21/31133

Abstract: Radiant energy may be applied to a photochemically susceptible etching or conditioning solution to enable precise control of the removal of material or alteration of the top surface of a wafer during the fabrication of semiconductor integrated circuits. A particular condition may be detected during the course of photoactivated generation of free radicals or molecular activation to control the further generation of said species by controlling the radiant energy exposure of a wafer.

Abstract translation: 辐射能量可以应用于光化学敏感的蚀刻或调理溶液，以在半导体集成电路的制造期间精确地控制材料的去除或晶片顶表面的改变。 在光活化产生自由基或分子活化的过程中可以检测到特定的条件，以通过控制晶片的辐射能量暴露来控制所述物质的进一步产生。

公开(公告)号：US20050074706A1

公开(公告)日：2005-04-07

申请号：US10679816

申请日：2003-10-06

Applicant: Robert Bristol ,  Heidi Cao ,  Manish Chandhok ,  Robert Meagley ,  Vijayakumar Ramachandrarao

Inventor： Robert Bristol ,  Heidi Cao ,  Manish Chandhok ,  Robert Meagley ,  Vijayakumar Ramachandrarao

IPC: G03F1/14 ,  G03F7/09 ,  G03F7/11 ,  G03F7/16 ,  G03F7/20 ,  G03F7/30 ,  G03F7/38 ,  G03F7/00

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F7/093 ,  G03F7/11 ,  G03F7/168 ,  G03F7/2002 ,  G03F7/3007 ,  G03F7/38

Abstract: Electric fields may be advantageously used in various steps of photolithographic processes. For example, prior to the pre-exposure bake, photoresists that have been spun-on the wafer may be exposed to an electric field to orient aggregates or other components within the unexposed photoresist. By aligning these aggregates or other components with the electric field, line edge roughness may be reduced, for example in connection with 193 nanometer photoresist. Likewise, during exposure, electric fields may be applied through uniquely situated electrodes or using a radio frequency coil. In addition, electric fields may be applied at virtually any point in the photolithography process by depositing a conductive electrode, which is subsequently removed during development. Finally, electric fields may be applied during the developing process to improve line edge roughness.

Abstract translation: 电场可以有利地用于光刻工艺的各个步骤。 例如，在预曝光烘烤之前，已经旋涂在晶片上的光致抗蚀剂可以暴露于电场以取向未曝光的光致抗蚀剂内的聚集体或其它组分。 通过将这些聚集体或其它组分与电场对准，可以减少线边缘粗糙度，例如与193纳米光致抗蚀剂结合。 同样地，在曝光期间，可以通过独特的电极或使用射频线圈施加电场。 此外，可以通过沉积导电电极在光刻工艺中的几乎任何点处施加电场，导电电极随后在显影期间被去除。 最后，可以在显影过程中施加电场以改善线边缘粗糙度。