公开(公告)号：US20150026407A1

公开(公告)日：2015-01-22

申请号：US13946125

申请日：2013-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Edward J. McLellan ,  Sudha Thiruvengadam ,  Douglas R. Beard ,  Carl D. Dietz ,  Stephen V. Kosonocky

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F1/3206 ,  G06F1/3275 ,  G06F12/0804 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13 ,  Y02D10/14

Abstract: As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache.

Abstract translation: 当处理器进入选择的低功耗模式时，通过将存储在高速缓存中的数据写入存储器层次结构的其他级别来缓冲数据。 高速缓存的刷新允许减小高速缓存的大小，而不会在将减少的高速缓存位置处的数据写入存储器层次结构方面带来额外的性能损失。 因此，当高速缓存退出所选择的低功率模式时，通过将高速缓存的路数设置为最小数量，将其设置为最小大小。 响应于处理系统处的定义的事件，高速缓存控制器改变每组高速缓存的路数。

公开(公告)号：US20140340114A1

公开(公告)日：2014-11-20

申请号：US13894014

申请日：2013-05-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald A. Priore ,  John G. Petrovick, JR. ,  Stephen V. Kosonocky ,  Robert S. Orefice

IPC: H03K19/003

CPC classification number: H03K19/003

Abstract: An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal.

Abstract translation: 集成电路装置包括用于分配第一信号的第一信号线。 第一信号线包括多个分支线，并且在每个分支线的末端定义叶节点。 第一逻辑耦合到叶节点并且可操作以产生指示对应于第一信号的信号线的叶节点的集体第一逻辑状态的第一状态信号。

公开(公告)号：US12271244B2

公开(公告)日：2025-04-08

申请号：US17390429

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Indrani Paul ,  Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Christopher T. Weaver

IPC: G06F9/24 ,  G06F1/3203 ,  G06F9/4401

Abstract: Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

公开(公告)号：US12235708B2

公开(公告)日：2025-02-25

申请号：US17483702

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry ,  Mihir Shaileshbhai Doctor

IPC: G06F1/32 ,  G06F1/3234

Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.

公开(公告)号：US12001265B2

公开(公告)日：2024-06-04

申请号：US17483694

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Thomas J. Gibney ,  Jose G. Cruz ,  Pravesh Gupta ,  Chintan S. Patel

IPC: G06F1/00 ,  G06F1/3234 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F1/3275 ,  G06F1/3265 ,  G06F3/0625 ,  G06F3/0635 ,  G06F3/0673 ,  G06F11/1469 ,  G06F2201/84

Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

公开(公告)号：US11936382B2

公开(公告)日：2024-03-19

申请号：US16454596

申请日：2019-06-27

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Joyce Cheuk Wai Wong ,  Dragoljub Ignjatovic ,  Mikhail Rodionov ,  Ljubisa Bajic ,  Stephen V. Kosonocky ,  Steven J. Kommrusch

IPC: H03L1/02 ,  H03K3/012 ,  H03K3/013 ,  H03K3/0231 ,  H03K3/03 ,  H03K5/15 ,  H03L5/00 ,  H03L7/085 ,  H03L7/099 ,  H03K5/1534

CPC classification number: H03K3/013 ,  H03K3/012 ,  H03K3/0231 ,  H03K3/03 ,  H03K5/1506 ,  H03K5/1508 ,  H03L1/02 ,  H03L5/00 ,  H03L7/085 ,  H03L7/0997 ,  H03K5/1534

Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

公开(公告)号：US20230315188A1

公开(公告)日：2023-10-05

申请号：US17710521

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  Indrani Paul ,  Benjamin Tsien ,  Stephen V. Kosonocky ,  John P. Petry ,  Christopher T. Weaver

IPC: G06F1/3234

CPC classification number: G06F1/3234

Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

公开(公告)号：US20180374853A1

公开(公告)日：2018-12-27

申请号：US15632765

申请日：2017-06-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Erhan Ergin ,  Dipanjan Sengupta ,  Elsie Lo ,  Stephen V. Kosonocky ,  Sree Rajesh Saha ,  Divya Guruja

IPC: H01L27/108 ,  H02M3/07 ,  H02M7/12 ,  H01L31/06 ,  G05F1/56 ,  G02B5/10 ,  H01L49/02

Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.

公开(公告)号：US09575553B2

公开(公告)日：2017-02-21

申请号：US14576924

申请日：2014-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Seng Oon Toh ,  Edward J. McLellan ,  Stephen V. Kosonocky ,  Michael Leonard Golden ,  Samuel D. Naffziger

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/04 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Abstract translation: 处理器在处理器处采用一组复制路径来确定处理器的工作频率和电压。 复制路径各自表示处理器的功能模块处的一个或多个电路路径。 复制路径上的延迟被归一化以增加复制路径准确地表示功能模块的电路路径的行为的可能性。 在归一化之后，通过在每个复制路径处改变复制路径的输出节点处的延迟，直到在复制路径的输出节点处的信号与在复制路径的延迟表示之间检测到不匹配来生成延迟值的分布 信号。 然后可以基于复制路径上的参考电压的变化来调整所得到的延迟值分布，以考虑由参考电压变化导致的电位分布误差。

公开(公告)号：US20160179186A1

公开(公告)日：2016-06-23

申请号：US14576924

申请日：2014-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Seng Oon Toh ,  Edward J. McLellan ,  Stephen V. Kosonocky ,  Michael Leonard Golden ,  Samuel D. Naffziger

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/04 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Abstract translation: 处理器在处理器处采用一组复制路径来确定处理器的工作频率和电压。 复制路径各自表示处理器的功能模块处的一个或多个电路路径。 复制路径上的延迟被归一化以增加复制路径准确地表示功能模块的电路路径的行为的可能性。 在归一化之后，通过在每个复制路径处改变复制路径的输出节点处的延迟，直到在复制路径的输出节点处的信号与在复制路径的延迟表示之间检测到不匹配来生成延迟值的分布 信号。 然后可以基于复制路径上的参考电压的变化来调整所得到的延迟值分布，以考虑由参考电压变化导致的电位分布误差。