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    DASHBOARD WITH PUSH MODEL FOR RECEIVING SENSOR DATA
    11.
    发明申请
    DASHBOARD WITH PUSH MODEL FOR RECEIVING SENSOR DATA 有权

    公开(公告)号：US20210048865A1

    公开(公告)日：2021-02-18

    申请号：US16543334

    申请日：2019-08-16

    Applicant: Apple Inc.

    Inventor： Achmed R. Zahir ,  Inder M. Sodhi ,  John H. Kelm

    IPC: G06F1/28 ,  G06F9/451 ,  G06F1/08

    Abstract: Systems, methods and mechanisms for efficiently reporting sensor data of multiple processing units. In various embodiments, a computing system includes processing units and a power management unit. The processing units include multiple sensors for measuring a variety of types of sensor data. If the sensor values exceed corresponding thresholds, then a processing unit sends the sensor values to the power management unit. Logic in the power management unit stores received sensor values. When the logic determines behavior of a processing unit changes, the logic updates one or more sensor thresholds for the processing unit for changing a frequency of reporting one or more sensor values of the processing unit. The logic sends the updated one or more sensor thresholds to the processing unit. The logic updates more operating modes and operating states for the processing units based on the received sensor values.

    FILTERING MEMORY CALIBRATION
    12.
    发明申请
    FILTERING MEMORY CALIBRATION 审中-公开

    公开(公告)号：US20200285406A1

    公开(公告)日：2020-09-10

    申请号：US16293398

    申请日：2019-03-05

    Applicant: Apple Inc.

    Inventor： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

    IPC: G06F3/06 ,  G11C11/4063 ,  G11C7/22

    Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

    Memory Controller Reservation of Retry Queue
    13.
    发明申请
    Memory Controller Reservation of Retry Queue 有权

    公开(公告)号：US20250103520A1

    公开(公告)日：2025-03-27

    申请号：US18819755

    申请日：2024-08-29

    Applicant: Apple Inc.

    Inventor： Ilya Granovsky ,  Jurgen M. Schulz ,  Tom Greenshtein ,  Elli Bagelman ,  Brian P. Lilly ,  John H. Kelm ,  Rohit K. Gupta ,  Sandeep Gupta ,  Anwar Q. Rohillah

    IPC: G06F13/16 ,  G06F12/0831

    Abstract: A memory controller circuit receives memory access requests from a network of a computer system. Entries are reserved for these requests in a retry queue circuit. An arbitration circuit of the memory controller circuit issues those requests to a tag pipeline circuit that determines whether the received memory access requests hit in a memory cache. As a memory access request passes through the tag pipeline circuit, it may require another pass through this pipeline—for example, if resources such as certain storage circuits needed to complete the memory access request are unavailable (for example a snoop queue circuit). The reservation that has been made in the retry queue circuit thus keeps the request from having to be returned to the network for resubmission to the memory controller circuit if initial processing of the memory access request cannot be completed.

    Multi-Processor Power Management Circuit
    14.
    发明申请
    Multi-Processor Power Management Circuit 有权

    公开(公告)号：US20250093937A1

    公开(公告)日：2025-03-20

    申请号：US18540798

    申请日：2023-12-14

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  John H. Kelm ,  Michael Bekerman

    IPC: G06F1/3234

    Abstract: A system includes a power management processor that may be configured to monitor operation of one or more circuit blocks in the system, and to determine a particular performance state of a set of performance states for one or more power domains in the system based on the monitored operation. The system further includes a performance management circuit that may be configured to receive, from the power management processor, an indication of the particular performance state. The performance management circuit may further be configured to determine a transition path from a current performance state to the particular performance state that avoids illegal performance state transitions, and to cause a control circuit to transition to the particular performance state using the transition path.

    Power Management Interface for Multiple Software Requestors
    15.
    发明申请
    Power Management Interface for Multiple Software Requestors 有权

    公开(公告)号：US20250093925A1

    公开(公告)日：2025-03-20

    申请号：US18540723

    申请日：2023-12-14

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  John H. Kelm ,  Josh P. de Cesare ,  Karl D. Wulcan ,  Michael Bekerman

    IPC: G06F1/26

    Abstract: An apparatus includes a control circuit, configured to transition a plurality of power domains into selected performance states, and a set of state request registers. A state request register may include fields that are associated with respective power domains. The apparatus may further include circuit blocks configured to store respective state request values into respective state request registers. A given state request value may indicate a requested performance state for at least one of the power domains. In addition, a performance management circuit may be configured to select, using the associated fields in the registers, a particular performance state for at least one of the power domains. The performance management circuit may be further configured to determine a transition path to sequence to the selected performance state, and to cause the control circuit to transition to the selected performance state using the transition path.

    Dashboard with push model for receiving sensor data
    17.
    发明授权
    Dashboard with push model for receiving sensor data 有权

    公开(公告)号：US11169585B2

    公开(公告)日：2021-11-09

    申请号：US16543334

    申请日：2019-08-16

    Applicant: Apple Inc.

    Inventor： Achmed R. Zahir ,  Inder M. Sodhi ,  John H. Kelm

    IPC: G06F1/28 ,  G06F9/451 ,  G06F1/08

    Abstract: Systems, methods and mechanisms for efficiently reporting sensor data of multiple processing units. In various embodiments, a computing system includes processing units and a power management unit. The processing units include multiple sensors for measuring a variety of types of sensor data. If the sensor values exceed corresponding thresholds, then a processing unit sends the sensor values to the power management unit. Logic in the power management unit stores received sensor values. When the logic determines behavior of a processing unit changes, the logic updates one or more sensor thresholds for the processing unit for changing a frequency of reporting one or more sensor values of the processing unit. The logic sends the updated one or more sensor thresholds to the processing unit. The logic updates more operating modes and operating states for the processing units based on the received sensor values.

    Datalogging circuit triggered by a watchdog timer
    18.
    发明授权
    Datalogging circuit triggered by a watchdog timer 有权

    公开(公告)号：US11853148B2

    公开(公告)日：2023-12-26

    申请号：US17656153

    申请日：2022-03-23

    Applicant: Apple Inc.

    Inventor： John H. Kelm ,  Richard H. Larson ,  Charles J. Fleckenstein

    IPC: G06F11/07

    CPC classification number: G06F11/0757

    Abstract: An apparatus includes a memory circuit, and an integrated circuit formed on a single semiconductor substrate and coupled to the memory circuit. The integrated circuit includes a watchdog timer, a plurality of functional circuits coupled together via a communication fabric, and a system management circuit coupled to the watchdog timer and to a subset of the functional circuits via respective dedicated point-to-point interfaces. A given functional circuit may be configured to repeatedly reset the watchdog timer before the watchdog timer expires. The system management circuit may be configured, in response to an expiration of the watchdog timer, to access information in the subset of the functional circuits via the respective point-to-point interfaces. The system management circuit may be further configured to store the accessed information in the memory circuit.

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