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公开(公告)号：US09548749B2
公开(公告)日：2017-01-17
申请号：US14531479
申请日：2014-11-03
Applicant: ARM Limited
Inventor： Paul Nicholas Whatmough , David Michael Bull
CPC classification number: H03L7/102 , H03L7/0992 , H03L2207/06
Abstract: An operating parameter method and circuitry are provided that generate operating parameter signals that are compensated for noise. Such operating parameter circuitry includes control loop circuitry that operates from a first power supply to provide an operating parameter signal to functional circuitry operating from a second power supply separate from the first power supply. The control loop circuitry comprises generator circuitry to generate the operating parameter signal based on an input signal. Replica generator circuitry operates from the second power supply to generate a further operating parameter signal based on the input signal. Adjustment circuitry performs a comparison on the operating parameter signal and the further operating parameter signal and causes an adjusted input signal to be produced in dependence on a result of the comparison. The adjusted input signal is received by the generator circuitry. Consequently, the generator circuitry is able to produce an operating parameter signal that has been compensated for noise in the circuit.
Abstract translation: 提供了一种操作参数方法和电路，其产生被补偿噪声的操作参数信号。 这种操作参数电路包括控制回路电路，其从第一电源操作，以向从与第一电源分开的第二电源操作的功能电路提供操作参数信号。 控制回路电路包括基于输入信号产生操作参数信号的发生器电路。 复制发生器电路从第二电源操作以基于输入信号生成另外的操作参数信号。 调整电路对操作参数信号和其他操作参数信号进行比较，并根据比较结果产生调整后的输入信号。 经调整的输入信号由发生器电路接收。 因此，发电机电路能够产生已经补偿了电路中的噪声的工作参数信号。
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公开(公告)号：US20140115376A1
公开(公告)日：2014-04-24
申请号：US14143065
申请日：2013-12-30
Applicant: ARM Limited
Inventor： Shidhartha DAS , David Michael Bull , Emre Ozer
IPC: G06F11/07
CPC classification number: G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.
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公开(公告)号：US12047083B2
公开(公告)日：2024-07-23
申请号：US17519490
申请日：2021-11-04
Applicant: Arm Limited
Inventor： El Mehdi Boujamaa , Benoit Labbe , David Michael Bull
CPC classification number: H03L7/091 , G06F1/08 , G06F1/12 , H03L7/0814
Abstract: In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.
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公开(公告)号：US11947460B2
公开(公告)日：2024-04-02
申请号：US17729233
申请日：2022-04-26
Applicant: Arm Limited
Inventor： Vladimir Vasekin , David Michael Bull , Vincent Rezard , Anton Antonov
IPC: G06F12/08 , G06F9/38 , G06F12/0842 , G06F12/0891
CPC classification number: G06F12/0842 , G06F9/3816 , G06F12/0891 , G06F2212/1021
Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.
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15.发明申请公开(公告)号：US20190163940A1
公开(公告)日：2019-05-30
申请号：US15825467
申请日：2017-11-29
Applicant: Arm Limited
Inventor： James Edward Myers , David Michael Bull , Edgar H. Callaway, JR.
Abstract: A method, system and surface covering for enabling wireless detection of damage to a structure is disclosed. At least one array having a plurality of nodes are coupled to a surface covering, such as at least one of a wall, ceiling and floor covering for a least a portion of the structure. An electronic reader is operable to wirelessly interrogate the array and read return signals from nodes in the array. The return signals contain data representing an ID for corresponding responsive nodes in the array, and the returned IDs are extracted and compared to a plurality of IDs stored in a data store for nodes in any given array. A mismatch between the returned and stored IDs for the nodes in the array indicates a structural defect in a respective portion of the structure overlaid by the floor/wall covering.
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Patent Agency Ranking
公开(公告)号：US20180233194A1
公开(公告)日：2018-08-16
申请号：US15948918
申请日：2018-04-09
Applicant: ARM Limited
Inventor： Parameshwarappa Anand Kumar Savanth , James Edward Myers , Pranay Prabhat , David Walter Flynn , Shidhartha Das , David Michael Bull
IPC: G11C11/419 , G11C5/06
CPC classification number: G11C11/419 , G11C5/063 , G11C11/4125
Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
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公开(公告)号：US09786362B1
公开(公告)日：2017-10-10
申请号：US15248335
申请日：2016-08-26
Applicant: ARM Limited
Inventor： Shidhartha Das , David Michael Bull , Pranay Prabhat , Adeline-Fleur Fleming
IPC: G11C8/00 , G11C11/419 , G11C11/418
CPC classification number: G11C11/419 , G11C5/14 , G11C7/18 , G11C11/413 , G11C11/418 , G11C2207/2236
Abstract: A memory circuit comprises an array of data storage elements; access circuitry to access a data bit, stored by a data storage element enabled for access, by an access signal for that data storage element; and control circuitry to enable groups of data storage elements for access, the groups having a group size, the group size being one or more, the access signals for data storage elements in a group being combined to provide a combined access signal common to that group of data storage elements; the control circuitry being configured to selectively operate in at least a first mode and a second mode, the group size in the first mode being different to the group size in the second mode.
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公开(公告)号：US10447412B2
公开(公告)日：2019-10-15
申请号：US15577487
申请日：2016-04-15
Applicant: ARM LIMITED
Inventor： Paul Nicholas Whatmough , George Smart , Shidhartha Das , David Michael Bull
IPC: H04B7/24 , H04B13/00 , H04B1/3827
Abstract: A device comprises a coupling configured to couple signals to and from a communications path including at least a part of a human or animal body; a data transmitter coupled to the coupling and configured to transmit, from time to time, a data signal of at least a predetermined temporal duration via the communications path; and a data receiver coupled to the coupling and configured to detect the presence of a signal on the communications path at sets of one or more successive detection instances disposed between successive transmissions of the data signal by the data transmitter, the data receiver being configured so that the successive detection instances of a set are temporally separated by no more than the predetermined temporal duration; the device being configured to initiate a processing operation in response to a detection by the data receiver of the presence of a signal on the communications path.
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公开(公告)号：US09933466B2
公开(公告)日：2018-04-03
申请号：US15172101
申请日：2016-06-02
Applicant: ARM Limited
Inventor： Paul Nicholas Whatmough , Shidhartha Das , David Michael Bull
Abstract: An apparatus and method are provided for detecting a resonant frequency giving rise to an impedance peak in a power delivery network used to provide a supply voltage. The apparatus includes resonant frequency detection circuitry that comprises test frequency control circuitry and a loading circuit. The test frequency control circuitry is arranged to generate control signals to indicate a sequence of test frequencies. A loading circuit is controlled by the control signals and operates from the supply voltage. In particular, in response to each test frequency indicated by the control signals, the loading circuit draws a duty-cycled current load through the power delivery network at that test frequency. Operation of the loading circuit produces a measurable property whose value varies in dependence on the supply voltage, thus enabling the resonant frequency to be determined from a variation in the value of that measurable property.
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公开(公告)号：US08862935B2
公开(公告)日：2014-10-14
申请号：US14143352
申请日：2013-12-30
Applicant: ARM Limited
Inventor： Shidhartha Das , David Michael Bull , Emre Ozer
IPC: G06F11/00 , G06F11/07 , G06F11/16 , G06F11/10 , G01R31/3181
CPC classification number: G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.
Abstract translation: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。
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