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公开(公告)号：US20190102175A1
公开(公告)日：2019-04-04
申请号：US15843965
申请日：2017-12-15
摘要： A hybrid floating-point arithmetic processor includes a scheduler, a hybrid register file, and a hybrid arithmetic operation circuit. The scheduler has an input for receiving floating-point instructions, and an output for providing decoded register numbers in response to the floating-point instructions. The hybrid register file is coupled to the scheduler and contains circuitry for storing a plurality of floating-point numbers each represented by a digital sign bit, a digital exponent, and an analog mantissa. The hybrid register file has an output for providing selected ones of the plurality of floating-point numbers in response to the decoded register numbers. The hybrid arithmetic operation circuit is coupled to the scheduler and to the hybrid register file, for performing a hybrid arithmetic operation between two floating-point numbers selected by the scheduler and providing a hybrid result represented by a result digital sign bit, a result digital exponent, and a result analog mantissa.
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公开(公告)号：US10152244B2
公开(公告)日：2018-12-11
申请号：US14840368
申请日：2015-08-31
发明人： David A. Roberts
摘要： Systems, apparatuses, and methods for utilizing a programmable memory command sequencer to generate multiple commands from a single memory request. A sequencer receives requests from a host processor and utilizes any of a plurality of programmable routines in response to determining that a given request meets specific criteria. A given programmable routine generates a plurality of memory commands which are then conveyed to a local memory controller and/or one or more remote memory controllers. The host processor programs the sequencer at boot time and updates the sequencer at runtime in response to changing application behavior. In various embodiments, the sequencer generates a variety of error correction routines in response to different requests received from the host processor.
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公开(公告)号：US20180300265A1
公开(公告)日：2018-10-18
申请号：US15490036
申请日：2017-04-18
摘要： Systems, apparatuses, and methods for routing traffic through vertically stacked memory are disclosed. A computing system includes a host processor die and multiple vertically stacked memory dies. The host processor die generates memory access requests for the data stored in the multiple memory array banks in the memory dies. At least one memory die uses an on-die network switch with a programmable routing table for routing packets corresponding to the generated memory requests. Routes use both vertical hops and horizontal hops to reach the target memory array bank and to avoid any congested or failed resources along the route. The vertically stacked memory dies use through silicon via interconnects and at least one via does not traverse through all of the memory dies. Accordingly, the host processor die does not have a direct connection to one or more of the multiple memory dies.
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公开(公告)号：US10090236B2
公开(公告)日：2018-10-02
申请号：US14995002
申请日：2016-01-13
IPC分类号： H01L23/498 , H01L21/48 , H01L23/14 , H01L23/15 , H01L25/065 , H01L25/00
摘要： The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.
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公开(公告)号：US09755964B2
公开(公告)日：2017-09-05
申请号：US14859844
申请日：2015-09-21
IPC分类号： H04L12/40 , H04L12/781 , H04L29/06 , H04L12/715 , H04L12/861
CPC分类号： H04L45/52 , H04L45/04 , H04L49/9057 , H04L69/08
摘要： A communication device includes a data source that generates data for transmission over a bus, and a data encoder that receives and encodes outgoing data. An encoder system receives outgoing data from a data source and stores the outgoing data in a first queue. An encoder encodes outgoing data with a header type that is based upon a header type indication from a controller and stores the encoded data that may be a packet or a data word with at least one layered header in a second queue for transmission. The device is configured to receive at a payload extractor, a packet protocol change command from the controller and to remove the encoded data and to re-encode the data to create a re-encoded data packet and placing the re-encoded data packet in the second queue for transmission.
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公开(公告)号：US09727241B2
公开(公告)日：2017-08-08
申请号：US14616058
申请日：2015-02-06
发明人： Gabriel H. Loh , David A. Roberts , Mitesh R. Meswani , Mark R. Nutter , John R. Slice , Prashant Nair , Michael Ignatowski
IPC分类号： G06F12/10 , G06F3/06 , G06F12/0893 , G06F12/1045
CPC分类号： G06F3/0604 , G06F3/0653 , G06F3/0673 , G06F12/0893 , G06F12/1027 , G06F12/1045 , G06F2212/60 , G06F2212/68
摘要： A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.
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17.发明授权公开(公告)号：US09698790B2
公开(公告)日：2017-07-04
申请号：US14751947
申请日：2015-06-26
发明人： David A. Roberts
IPC分类号： H03K19/17 , H03K19/00 , G06F15/78 , H03K19/177
CPC分类号： H03K19/17728 , G06F15/7892 , H03K19/0008 , H03K19/1776 , H03K19/17776
摘要： A programmable device comprises one or more programming regions, each comprising a plurality of configurable logic blocks, where each of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block via a programmable interconnect fabric. The programmable device further comprises configuration logic configured to, in response to an instruction in an instruction stream, reconfigure hardware in one or more of the configurable logic blocks in a programming region independently from any of the other programming regions.
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公开(公告)号：US20170060450A1
公开(公告)日：2017-03-02
申请号：US14840368
申请日：2015-08-31
发明人： David A. Roberts
CPC分类号： G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1068 , G06F11/2058 , G06F11/2087
摘要： Systems, apparatuses, and methods for utilizing a programmable memory command sequencer to generate multiple commands from a single memory request. A sequencer receives requests from a host processor and utilizes any of a plurality of programmable routines in response to determining that a given request meets specific criteria. A given programmable routine generates a plurality of memory commands which are then conveyed to a local memory controller and/or one or more remote memory controllers. The host processor programs the sequencer at boot time and updates the sequencer at runtime in response to changing application behavior. In various embodiments, the sequencer generates a variety of error correction routines in response to different requests received from the host processor.
摘要翻译： 用于利用可编程存储器命令定序器从单个存储器请求生成多个命令的系统，装置和方法。 响应于确定给定请求满足特定标准，定序器从主机处理器接收请求并且利用多个可编程例程中的任何一个。 给定的可编程程序产生多个存储器命令，然后将其传送到本地存储器控制器和/或一个或多个远程存储器控制器。 主机处理器在启动时对序列器进行编程，并在运行时更新序列器以响应不断变化的应用程序行为。 在各种实施例中，定序器响应于从主机处理器接收到的不同请求而生成各种纠错程序。
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公开(公告)号：US09535627B2
公开(公告)日：2017-01-03
申请号：US14044454
申请日：2013-10-02
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/068 , G06F13/1642 , G06F13/1668 , Y02D10/14
摘要： A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.
摘要翻译： 提供了一种用于访问异构存储器系统的系统，方法和计算机可读存储设备。 存储器控制器基于与命令相关联的访问优先级来调度对一组存储器区域中的存储器区域的访问，并且其中该组存储器区域具有相应的访问延迟。 存储器控制器还使用至少两个队列和访问优先级来延迟对该组存储器区域的访问。
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公开(公告)号：US20160378668A1
公开(公告)日：2016-12-29
申请号：US14747967
申请日：2015-06-23
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A memory module stores memory access metadata reflecting information about memory accesses to the memory module. The memory access metadata can indicate the number of times a particular unit of data (e.g., a row of data, a unit of data corresponding to a cache line, and the like) has been read, written, had one or more of its bits flipped, and the like. Modifications to the embedded access metadata can be made by a control module at the memory module itself, thereby reducing overhead at a processor core. In addition, the control module can be configured to record different access metadata for different memory locations of the memory module.
摘要翻译： 存储器模块存储反映关于存储器模块的存储器访问的信息的存储器访问元数据。 存储器访问元数据可以指示已读取，写入的特定数据单元（例如，一行数据，对应于高速缓存行等的数据单元等）的次数具有其位中的一个或多个 翻转等。 嵌入式访问元数据的修改可以由存储器模块本身的控制模块进行，从而减少处理器核心的开销。 此外，控制模块可以被配置为记录存储器模块的不同存储器位置的不同访问元数据。
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