公开(公告)号：US20170018550A1

公开(公告)日：2017-01-19

申请号：US14801730

申请日：2015-07-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Hsu-Chiang SHIH ,  Sheng-Chi HSIEH ,  Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L27/08 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01G4/30 ,  H01L23/481 ,  H01L27/101 ,  H01L28/60 ,  H01L2224/18

Abstract: A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.

Abstract translation: 对半导体装置及其制造方法进行说明。 半导体器件包括衬底，第一电容器和第二电容器。 第一电容器包括第一导电层，第一绝缘层和第二导电层。 第一导电层设置在基板上。 第一绝缘层设置在第一导电层上并具有第一周边边缘。 第二导电层设置在第一绝缘层上并具有第二周边。 第二电容器包括第三导电层，第二绝缘层和第二导电层。 第二绝缘层设置在第二导电层上并具有第三外围边缘。 第三导电层设置在第二绝缘层上并具有第四周边。 第一，第二，第三和第四外围边缘彼此对准。

公开(公告)号：US20210043719A1

公开(公告)日：2021-02-11

申请号：US17083281

申请日：2020-10-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L49/02 ,  H01L23/522

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

公开(公告)号：US20190393297A1

公开(公告)日：2019-12-26

申请号：US16447839

申请日：2019-06-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Chien-Hua CHEN ,  Teck-Chong LEE ,  Hung-Yi LIN ,  Pao-Nan LEE ,  Hsin Hsiang WANG ,  Min-Tzu HSU ,  Po-Hao CHEN

IPC: H01L49/02 ,  H01L25/16 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

公开(公告)号：US20190055118A1

公开(公告)日：2019-02-21

申请号：US15680056

申请日：2017-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Cheng-Yuan KUNG ,  Che-Hau HUANG ,  Chin-Cheng KUO

IPC: B81B7/00 ,  B81C1/00

Abstract: A Micro Electro-Mechanical System (MEMS) device package includes a first circuit layer, a partition wall, a MEMS component, a second circuit layer and a polymeric dielectric layer. The partition wall is disposed over the first circuit layer. The MEMS component is disposed over the partition wall and electrically connected to the first circuit layer. The first circuit layer, the partition wall and the MEMS component enclose a space. The second circuit layer is disposed over and electrically connected to the first circuit layer. The polymeric dielectric layer is disposed between the first circuit layer and the second circuit layer.

公开(公告)号：US20180358291A1

公开(公告)日：2018-12-13

申请号：US15618085

申请日：2017-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Sheng-Chi HSIEH ,  Cheng-Yuan KUNG

IPC: H01L23/498 ,  H05K1/16 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H05K1/162

Abstract: A method for manufacturing a semiconductor device package includes providing a substrate having a first surface and a second surface opposite to the first surface; disposing a passive component layer on the first surface of the substrate; after disposing the passive component layer, forming at least one via in the substrate, wherein the via penetrates the substrate and the passive component layer; and disposing a conductive layer on the passive component layer and filling the via with the conductive layer.

公开(公告)号：US20180358290A1

公开(公告)日：2018-12-13

申请号：US15618084

申请日：2017-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Ming-Hung CHEN ,  Hsu-Chiang SHIH

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/16 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H05K1/162

Abstract: A semiconductor device package includes a substrate, a first insulation layer, a support film and an interconnection structure. The substrate has a first sidewall, a first surface and a second surface opposite to the first surface. The first insulation layer is on the first surface of the substrate and has a second sidewall. The first insulation layer has a first surface and a second surface adjacent to the substrate and opposite to the first surface of the first insulation layer. The support film is on the second surface of the substrate and has a third sidewall. The support film has a first surface adjacent to the substrate and a second surface opposite to the first surface of the support film. The interconnection structure extends from the first surface of the first insulation layer to the second surface of the support film via the first insulation layer and the support film. The interconnection structure covers the first, second and third sidewalls.

公开(公告)号：US20180247904A1

公开(公告)日：2018-08-30

申请号：US15442492

申请日：2017-02-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Chi HSIEH ,  Hung-Yi LIN ,  Cheng-Yuan KUNG ,  Pao-Nan LEE ,  Chien-Hua CHEN

IPC: H01L23/66 ,  H03H1/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/642 ,  H01L23/645 ,  H01L2223/6616 ,  H01L2223/6672 ,  H03H3/02 ,  H03H3/08 ,  H03H9/0523 ,  H03H9/0557 ,  H03H9/1014 ,  H03H9/1071

Abstract: The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a substrate, at least one die, a sealing ring and an inductor. The at least one die is mounted on the substrate and includes a plurality of component structures operating with acoustic waves. The component structures are arranged on a side of the at least one die that faces the substrate. The sealing ring is disposed between the at least one die and the substrate and surrounds the component structures. The inductor is disposed in the substrate.

公开(公告)号：US20180138262A1

公开(公告)日：2018-05-17

申请号：US15351265

申请日：2016-11-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/147 ,  H01L23/15 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13111 ,  H01L2924/14

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

公开(公告)号：US20170133360A1

公开(公告)日：2017-05-11

申请号：US15406530

申请日：2017-01-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Teck-Chong LEE ,  Chien-Hua CHEN ,  Yung-Shun CHANG ,  Pao-Nan LEE

IPC: H01L27/01 ,  H01L23/528 ,  H01L21/70 ,  H01L49/02

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/707 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/4813 ,  H05K1/0306 ,  H05K1/185 ,  H05K2201/0154

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

公开(公告)号：US20150349048A1

公开(公告)日：2015-12-03

申请号：US14724522

申请日：2015-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Teck-Chong LEE ,  Chien-Hua CHEN ,  Yung-Shun CHANG ,  Pao-Nan LEE

IPC: H01L49/02 ,  H01L21/283

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/707 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/4813 ,  H05K1/0306 ,  H05K1/185 ,  H05K2201/0154

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

Abstract translation: 半导体器件包括衬底，种子层，第一图案化金属层，电介质层和第二金属层。 种子层设置在基板的表面上。 第一图案化金属层设置在种子层上并具有第一厚度。 第一图案化金属层包括第一部分和第二部分。 电介质层设置在第一图案化金属层的第一部分上。 第二金属层设置在电介质层上，具有第二厚度，其中第一厚度大于第二厚度。 第一图案化金属层的第一部分，电介质层和第二金属层形成电容器。 第一图案化金属层的第一部分是电容器的下电极，第一图案化金属层的第二部分是电感器。