公开(公告)号：US20190027441A1

公开(公告)日：2019-01-24

申请号：US15652821

申请日：2017-07-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kun-Ming CHEN ,  Yuan-Feng CHIANG

IPC: H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L25/00

Abstract: An interposer comprises a first conductive wire having a first terminal and a second terminal, a first oxide layer, and an encapsulant. The first oxide layer covers the first conductive wire and exposes the first terminal and the second terminal of the first conductive wire. The encapsulant covers the first oxide layer and exposes the first terminal and the second terminal of the first conductive wire.

公开(公告)号：US20220367304A1

公开(公告)日：2022-11-17

申请号：US17317770

申请日：2021-05-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuoching CHENG ,  Yuan-Feng CHIANG ,  Ya Fang CHAN ,  Wen-Long LU ,  Shih-Yu WANG

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/16 ,  H01L23/538 ,  H01L21/56

Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.

公开(公告)号：US20220084958A1

公开(公告)日：2022-03-17

申请号：US17537317

申请日：2021-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Peng YANG ,  Yuan-Feng CHIANG ,  Po-Wei LU

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/16

Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.

公开(公告)号：US20200271942A1

公开(公告)日：2020-08-27

申请号：US16872052

申请日：2020-05-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Feng CHIANG ,  Tsung-Tang TSAI ,  Min Lung HUANG

IPC: G02B27/30 ,  G02B5/00 ,  G02B19/00

Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.

公开(公告)号：US20180342473A1

公开(公告)日：2018-11-29

申请号：US15605897

申请日：2017-05-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Yuan-Feng CHIANG ,  Tsung-Tang TSAI

IPC: H01L23/00

Abstract: A via structure includes a base material, a first dielectric layer and a second dielectric layer. The base material includes a first surface and a second surface opposite to the first surface, and defines at least one through hole. The first dielectric layer is disposed on the first surface of the base material and includes a gradient surface exposed in the through hole of the base material. The second dielectric layer is disposed on the gradient surface of first dielectric layer.

公开(公告)号：US20180061767A1

公开(公告)日：2018-03-01

申请号：US15692947

申请日：2017-08-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Feng CHIANG ,  Cong-Wei CHEN ,  I-Ting CHI ,  Shao-An CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/065 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/96

Abstract: A semiconductor package structure includes a semiconductor substrate, at least one semiconductor die, an encapsulant, a protection layer, a plurality of conductive elements and a redistribution layer. The semiconductor die is disposed on the semiconductor substrate. The encapsulant covers at least a portion of the semiconductor die, and has a first surface and a lateral surface. The protection layer covers the first surface and the lateral surface of the encapsulant. The conductive elements surround the lateral surface of the encapsulant. The redistribution layer electrically connects the semiconductor die and the conductive elements.

公开(公告)号：US20170207151A1

公开(公告)日：2017-07-20

申请号：US14995572

申请日：2016-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Chi-Chang LEE ,  Wei-Min HSIAO ,  Yuan-Feng CHIANG

IPC: H01L23/495 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49572 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/147 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/81

Abstract: A semiconductor package structure includes a conductive structure, at least two semiconductor elements and an encapsulant. The conductive structure has a first surface and a second surface opposite the first surface. The semiconductor elements are disposed on and electrically connected to the first surface of the conductive structure. The encapsulant covers the semiconductor elements and the first surface of the conductive structure. The encapsulant has a width ‘L’ and defines at least one notch portion. A minimum distance ‘d’ is between a bottom surface of the notch portion and the second surface of the conductive structure. The encapsulant has a Young's modulus ‘E’ and a rupture strength ‘Sr’, and L/(K×d)>E/Sr, wherein ‘K’ is a stress concentration factor with a value of greater than 1.2.