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    Transaction ordering management
    12.
    发明授权
    Transaction ordering management 有权

    公开(公告)号：US11748285B1

    公开(公告)日：2023-09-05

    申请号：US16452233

    申请日：2019-06-25

    Applicant: Amazon Technologies, Inc.

    Inventor： Roi Ben Haim ,  Guy Nakibly ,  Adi Habusha ,  Simaan Bahouth

    IPC: G06F13/38 ,  G06F9/455 ,  G11C7/10 ,  H04L69/22

    CPC classification number: G06F13/387 ,  G06F9/45533 ,  G11C7/1006 ,  H04L69/22 ,  G06F2213/0026

    Abstract: Ordering rules, such as those enforced by the peripheral component interconnect express (PCIe) protocol for data communications, can be intelligently enforced for independent transactions. A single device might host or be associated with multiple PCIe devices, such as virtual machines, and treating requests from these separate PCIe devices as coming from separate domains enables the ordering rules to be bypassed for certain transactions. Further, since a virtual machine might host multiple applications or be associated with multiple processors that can submit independent requests, the ordering rules can be bypassed at the transaction level in at least some instances. The ability to intelligently bypass ordering rules can help to improve the performance of the overall system, as requests do not need to be unnecessarily delayed and data storage capacity can be more fully utilized.

    Memory data migration hardware
    13.
    发明授权
    Memory data migration hardware 有权

    公开(公告)号：US11620233B1

    公开(公告)日：2023-04-04

    申请号：US16588898

    申请日：2019-09-30

    Applicant: Amazon Technologies, Inc.

    Inventor： Adi Habusha ,  Ali Ghassan Saidi ,  Tzachi Zidenberg

    IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/0891 ,  G06F3/06 ,  G06F9/30

    Abstract: An integrated circuit for offloading a page migration operation from a host processor is provided. The integrated circuit is configured to: receive, from the host processor, a request to perform the page migration operation from a first physical address to a second physical address; and based on the request, perform the page migration operation. The page migration operation comprises: performing a copy operation of data from the first physical address to the second physical address, and updating a page table entry based on the second physical address, to enable the host processor to access the data from the second physical address based on the updated page table entry.

    Low-latency wake-up in a peripheral device
    17.
    发明授权
    Low-latency wake-up in a peripheral device 有权

    公开(公告)号：US10409744B1

    公开(公告)日：2019-09-10

    申请号：US15251877

    申请日：2016-08-30

    Applicant: Amazon Technologies, Inc.

    Inventor： Saar Gross ,  Said Bshara ,  Adi Habusha ,  Nafea Bshara ,  Ronen Shitrit

    IPC: G06F1/32 ,  G06F13/24 ,  G06F13/42 ,  G06F1/3287 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/3293

    Abstract: A processor in a peripheral device can include a wait-for-event mechanism, through which the processor can enter low-power mode and be woken from lower-power mode with an event. Using an event, rather than an interrupt, allows the processor to wake without the latency incurred by an interrupt handling routine. In various implementations, the processor may be configured to execute a sequence of instructions that include a wait-for-event instruction. The wait-for-event instruction can be called when the processor is idle. The wait-for-event instruction may initiate a low-power mode for the processor, wherein the processor suspends executing the sequence of instructions. The processor may further be configured to receive, at an event input, an event signal. The event signal may cause the processor to exit the low-power mode and to resume executing the sequence of instructions from the point at which the processor suspended executing the sequence of instructions.

    Hybrid hardware and software reporting management
    18.
    发明授权
    Hybrid hardware and software reporting management 有权

    公开(公告)号：US10360092B1

    公开(公告)日：2019-07-23

    申请号：US15597987

    申请日：2017-05-17

    Applicant: Amazon Technologies, Inc.

    Inventor： Hani Ayoub ,  Adi Habusha ,  Itay Poleg

    IPC: G06F11/07 ,  H03M13/00

    Abstract: A hybrid approach using hardware and software is used for report management in peripheral component interconnect (PCI) express devices. The device hardware detects an error associated with a transaction with a host computer. The device software identifies a function associated with the error and determines various attributes of the error. The device software then exposes the attributes of the error in the PCI express and the advanced error reporting (AER) capabilities. The error can be reported in a message transaction to the host computer.

    Adapter device for large address spaces
    19.
    发明授权
    Adapter device for large address spaces 有权

    公开(公告)号：US10255213B1

    公开(公告)日：2019-04-09

    申请号：US15083113

    申请日：2016-03-28

    Applicant: Amazon Technologies, Inc.

    Inventor： Adi Habusha ,  Itai Avron ,  Yaakov Gendel

    IPC: G06F13/38 ,  G06F13/40 ,  G06F5/10 ,  G06F3/06

    Abstract: Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a sequential address buffer and a memory. A region of the memory may be configured as a data block, which may be associated with an address range. The address range may correspond to a region of an address space of a target device. The adapter device may be configured to receive a write transaction, the write transaction having an address and data. The adapter device may further write the address to the sequential address buffer. The adapter device may further determine that the address is within the address range, and to write the data to the data block. The adapter device may further, upon the occurrence of an event, write the data from the data block to the region of the address space of the target device.

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