公开(公告)号：US10056914B2

公开(公告)日：2018-08-21

申请号：US15282586

申请日：2016-09-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： Zhao Li ,  Hajime Shibata ,  Trevor Clifford Caldwell ,  Richard E. Schreier ,  Victor Kozlov ,  David Nelson Alldred ,  Prawal Man Shrestha

IPC: H03M1/10 ,  H03M1/36 ,  H03M3/00

CPC classification number: H03M1/1023 ,  H03M1/1004 ,  H03M1/1038 ,  H03M1/1085 ,  H03M1/361 ,  H03M3/378 ,  H03M3/384

Abstract: A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

公开(公告)号：US09912342B2

公开(公告)日：2018-03-06

申请号：US15369175

申请日：2016-12-05

Applicant: Analog Devices Global

Inventor： Zhao Li ,  Hajime Shibata ,  Trevor Clifford Caldwell ,  Yunzhi Dong ,  Jialin Zhao ,  Richard E. Schreier ,  Victor Kozlov ,  David Nelson Alldred ,  Prawal Man Shrestha

IPC: H03M1/10 ,  H03M1/34 ,  H03M1/12 ,  H03M1/06 ,  H03M3/00

CPC classification number: H03M1/1009 ,  H03M1/0626 ,  H03M1/066 ,  H03M1/1245 ,  H03M1/34 ,  H03M3/388 ,  H03M3/422

Abstract: An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.

公开(公告)号：US09838031B2

公开(公告)日：2017-12-05

申请号：US15360984

申请日：2016-11-23

Applicant: Analog Devices Global

Inventor： Yunzhi Dong ,  Hajime Shibata ,  Trevor Clifford Caldwell ,  Zhao Li ,  Jialin Zhao ,  Jose Barreiro Silva

IPC: H03M3/00 ,  H03M1/36

CPC classification number: H03M3/422 ,  H03M1/361 ,  H03M3/322 ,  H03M3/344 ,  H03M3/378 ,  H03M3/388 ,  H03M3/414 ,  H03M3/436 ,  H03M3/464

Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.

公开(公告)号：US09793908B2

公开(公告)日：2017-10-17

申请号：US15360816

申请日：2016-11-23

Applicant: Analog Devices Global

Inventor： Hajime Shibata

IPC: H03M1/06 ,  H02H9/04 ,  H03M1/12 ,  H03K17/082 ,  H03M3/00

CPC classification number: H03M1/06 ,  H02H9/04 ,  H03K17/0822 ,  H03M1/129 ,  H03M3/322 ,  H03M3/414 ,  H03M3/458

Abstract: Continuous-time analog-to-digital converters (ADCs) such as continuous-time delta-sigma ADCs and continuous-time pipeline ADCs, has input resistor structure at the input. The input resistor structure is typically tunable, and the tunability is usually provided by metal-oxide semiconductor field effect transistor (MOSFET) switches. Core MOSFETs, which has a terminal-to-terminal voltage

公开(公告)号：US09768793B2

公开(公告)日：2017-09-19

申请号：US15365867

申请日：2016-11-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： Qingdong Meng ,  Hajime Shibata ,  Richard E. Schreier ,  Martin Steven McCormick ,  Yunzhi Dong ,  Jose Barreiro Silva ,  Jialin Zhao ,  Donald W. Paterson ,  Wenhua W. Yang

IPC: H03M3/00 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03M1/08 ,  H03M1/124 ,  H03M3/344 ,  H03M3/414

Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

公开(公告)号：US09432045B2

公开(公告)日：2016-08-30

申请号：US14524729

申请日：2014-10-27

Applicant: ANALOG DEVICES GLOBAL

Inventor： Hajime Shibata

IPC: H03M1/38 ,  H03M1/44 ,  H03M1/12 ,  H03M1/00 ,  H03M1/16

CPC classification number: H03M1/44 ,  H03M1/001 ,  H03M1/002 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/167

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract translation: A转换器可以包括串联连接的多个转换器级。 每个转换器级可以接收时钟信号和模拟输入信号，并且可以产生模拟输出信号和数字输出信号。 每个转换器级可以包括产生数字输出信号的编码器，产生重构信号的解码器，产生延迟信号的延迟转换器和产生残差信号的放大器，其中延迟信号可以是连续电流信号。