公开(公告)号：US10298511B2

公开(公告)日：2019-05-21

申请号：US15246046

申请日：2016-08-24

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Christopher D. Shuler ,  Benjamin K. Dodge ,  Thejasvi M. Vijayaraj ,  Harshavardhan Kaushikkar ,  Yang Yang ,  Rong Z. Hu ,  Srinivasa R. Sridharan ,  Wolfgang H. Klingauf ,  Neeraj Parik

IPC: H04W72/12 ,  H04L12/863 ,  G06F13/16 ,  G06F9/54 ,  H04L12/865

Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

公开(公告)号：US20180063016A1

公开(公告)日：2018-03-01

申请号：US15246046

申请日：2016-08-24

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Christopher D. Shuler ,  Benjamin K. Dodge ,  Thejasvi M. Vijayaraj ,  Harshavardhan Kaushikkar ,  Yang Yang ,  Rong Z. Hu ,  Srinivasa R. Sridharan ,  Wolfgang H. Klingauf ,  Neeraj Parik

IPC: H04L12/863

CPC classification number: H04L47/6295 ,  G06F9/546 ,  G06F13/1642 ,  H04L47/6275

Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

公开(公告)号：US09891853B1

公开(公告)日：2018-02-13

申请号：US15000626

申请日：2016-01-19

Applicant: Apple Inc.

Inventor： Neeraj Parik ,  Gurjeet S. Saund ,  Rakesh L. Notani ,  Robert E. Jeter

IPC: G06F3/06 ,  G11C7/22 ,  G06F13/16

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1689 ,  G11C7/222 ,  G11C2207/2254

Abstract: A method and apparatus for selective calibrations of a memory subsystem is disclosed. The memory subsystem includes a memory and a memory controller. The memory controller is configured to periodically perform calibrations of a data strobe signal conveyed to the memory and a reference voltage used to distinguish between a logic 0 and a logic 1. The memory subsystem is also coupled to receive a clock signal (e.g., at the memory controller). If a pending change of frequency of the clock signal is indicated to the memory controller during performance of a periodic calibration, the reference voltage calibration may be aborted prior to or during the performance thereof, while the data strobe calibration may be completed.

公开(公告)号：US20160364345A1

公开(公告)日：2016-12-15

申请号：US14738265

申请日：2015-06-12

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Neeraj Parik

IPC: G06F13/16 ,  G11C8/18 ,  G11C7/10 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F13/161 ,  G06F12/023 ,  G06F12/0646 ,  G06F2212/1044 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: In some embodiments, a memory interface system includes a memory interface circuit and a memory controller. The memory interface circuit is configured to communicate with a memory device. The memory controller is configured, in response to the memory device operating at a first frequency, to store configuration information corresponding to the memory device operating at a second frequency. The memory controller is further configured, in response to the memory device transitioning to the second frequency, to send the configuration information to the memory interface circuit. In some embodiments, storing the configuration information may result in some memory requests being provided to the memory device more quickly, as compared to a different memory interface system where the configuration information is not stored at the memory controller. Additionally, in some embodiments, storing the configuration information may result in the configuration information being transmitted to the memory interface circuit more efficiently.

Abstract translation: 在一些实施例中，存储器接口系统包括存储器接口电路和存储器控制器。 存储器接口电路被配置为与存储器件通信。 存储器控制器被配置为响应于以第一频率工作的存储器件来存储与在第二频率下操作的存储器件对应的配置信息。 存储器控制器还被配置为响应于存储器件转换到第二频率，将配置信息发送到存储器接口电路。 在一些实施例中，存储配置信息可能导致与其中配置信息未被存储在存储器控制器的不同的存储器接口系统相比更快地提供给存储器设备的一些存储器请求。 此外，在一些实施例中，存储配置信息可以导致更有效地将配置信息发送到存储器接口电路。

公开(公告)号：US09384820B1

公开(公告)日：2016-07-05

申请号：US14738119

申请日：2015-06-12

Applicant: Apple Inc.

Inventor： Neeraj Parik ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1636 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4096 ,  G11C2211/4061

Abstract: A method and apparatus for aligning calibration segments for increased availability of a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto via a number of independently operable channels (interfaces). The memory controller may convey on each of the channels at least one corresponding data strobe signal. The data strobe signal in each channel may be periodically calibrated. The memory controller may be configured to align the periodic calibrations in time so that they are performed concurrently instead of in a staggered manner. During the time the calibrations are performed on each channel, the memory may be unavailable for normal accesses.

Abstract translation: 公开了一种用于对准校准段以提高存储器子系统的可用性的方法和装置。 在一个实施例中，存储器子系统包括存储器和经由多个可独立操作的通道（接口）耦合到其上的存储器控​​制器。 存储器控制器可以在每个通道上传送至少一个对应的数据选通信号。 可以周期地校准每个通道中的数据选通信号。 存储器控制器可以被配置为在时间上对准周期性校准，使得它们同时执行而不是以交错方式执行。 在每个通道执行校准时，存储器可能无法正常访问。

公开(公告)号：US20160034219A1

公开(公告)日：2016-02-04

申请号：US14450525

申请日：2014-08-04

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Neeraj Parik ,  Kai Lun Hsiung

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0683 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1689

Abstract: A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit.The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. The memory interface unit may be configured to operate in a normal mode and a low power mode. However, in response to an occurrence of a given predetermined interval while the memory interface unit is in the low power mode, the memory interface unit may be configured to calibrate the timing unit subsequent to transitioning to the normal mode.

Abstract translation: 系统包括具有一个或多个存储阵列的存储器单元，以及可以耦合在存储器控制器和存储器单元之间的存储器接口单元。 存储器接口单元可以包括可以生成用于控制对存储器单元的读取和写入访问的定时信号的定时单元，以及可以以预定间隔校准定时单元的控制单元。 存储器接口单元可以被配置为在正常模式和低功率模式下操作。 然而，响应于在存储器接口单元处于低功率模式时发生给定的预定间隔，存储器接口单元可以被配置为在转换到正常模式之后校准定时单元。