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    Programmable mapping of guard tag storage locations
    11.
    发明授权
    Programmable mapping of guard tag storage locations 有权

    公开(公告)号：US11762566B2

    公开(公告)日：2023-09-19

    申请号：US17370291

    申请日：2021-07-08

    Applicant: Arm Limited

    Inventor： Richard Roy Grisenthwaite ,  Graeme Peter Barnes

    IPC: G06F3/06

    CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0673

    Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions, and memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. The memory access circuitry determines, according to a programmable mapping, a mapping of guard tag storage locations for storing guard tags for corresponding blocks of memory locations.

    Apparatus and method including an ownership table for indicating owner processes for blocks of physical addresses of a memory
    13.
    发明授权
    Apparatus and method including an ownership table for indicating owner processes for blocks of physical addresses of a memory 有权

    公开(公告)号：US11314658B2

    公开(公告)日：2022-04-26

    申请号：US15574596

    申请日：2016-04-28

    Applicant: ARM LIMITED

    Inventor： Jason Parker ,  Richard Roy Grisenthwaite ,  Andrew Christopher Rose

    IPC: G06F12/1036 ,  G06F12/02 ,  G06F12/14 ,  G06F12/10 ,  G06F9/455 ,  G06F12/1009

    Abstract: A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses. A descriptor table may be used to store process state identifiers, where the process states may include invalid, prepare and execute states. The processes may comprise a hypervisor and/or a virtual machine (VM).

    Apparatus and method for mapping architectural registers to physical registers
    17.
    发明授权
    Apparatus and method for mapping architectural registers to physical registers 有权
    将架构寄存器映射到物理寄存器的装置和方法

    公开(公告)号：US09311088B2

    公开(公告)日：2016-04-12

    申请号：US13927552

    申请日：2013-06-26

    Applicant: ARM Limited

    Inventor： Frederic Claude Marie Piry ,  Louis-Marie Vincent Mouton ,  Luca Scalabrino ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455

    CPC classification number: G06F9/30098 ,  G06F9/3012 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/45558

    Abstract: An apparatus and method are provided for performing register renaming. Available register identifying circuitry is provided to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration data whose value is modified during operation of the processing circuitry is stored such that, when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The register identifying circuitry is arranged to reference the modified data value, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers.

    Abstract translation: 提供了一种用于执行寄存器重命名的装置和方法。 提供可用的寄存器识别电路以识别哪些物理寄存器形成可由寄存器重命名电路映射到由要执行的指令指定的架构寄存器的物理寄存器池。 存储其值在处理电路的操作期间被修改的配置数据，使得当配置数据具有第一值时，配置数据识别架构寄存器集合的至少一个体系结构寄存器，其不需要映射到物理寄存器 寄存器重命名电路。 寄存器识别电路被布置为引用修改的数据值，使得当配置数据具有第一值时，由于需要映射到物理寄存器的架构寄存器的数量的减少，池中的物理寄存器的数量增加 。

    Communication of message signalled interrupts
    19.
    发明授权
    Communication of message signalled interrupts 有权
    消息信号中断的通信

    公开(公告)号：US08924615B2

    公开(公告)日：2014-12-30

    申请号：US13661456

    申请日：2012-10-26

    Applicant: ARM Limited

    Inventor： Richard Roy Grisenthwaite ,  Anthony Jebson ,  Andrew Christopher Rose ,  Matthew Lucien Evans

    IPC: G06F13/26 ,  G06F13/24

    CPC classification number: G06F13/26 ,  G06F13/24

    Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

    Abstract translation: 提供全局中断号码空间38用于消息信号中断。 中断目的地10,12,14,16提供有等待中断高速缓存24，其中由全局挂起状态存储器34提供的后备存储器由全部高速缓存或独立的各个未决状态存储器56共享。中断号码空间可以被划分为具有 可编程映射数据用于指示哪些中断目的地负责哪些区域。 当中断从一个中断目的地迁移到另一个中断时，这种可编程映射数据被更新。 在重新分配过程期间，待处理的中断可以被刷新回到全局挂起状态存储器34，使得该待决中断数据可以被新负责的中断目的地拾取。

    Deferred system error exception handling in a data processing apparatus
    20.
    发明授权
    Deferred system error exception handling in a data processing apparatus 有权

    公开(公告)号：US11461104B2

    公开(公告)日：2022-10-04

    申请号：US14952807

    申请日：2015-11-25

    Applicant: ARM LIMITED

    Inventor： Michael John Williams ,  Richard Roy Grisenthwaite ,  Simon John Craske

    IPC: G06F9/38 ,  G06F9/52 ,  G06F11/07

    Abstract: Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition.

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