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公开(公告)号：US09881941B2
公开(公告)日：2018-01-30
申请号：US14498282
申请日：2014-09-26
Inventor： Zhenyu Xie
IPC: H01L27/12
CPC classification number: H01L27/124 , H01L27/1248 , H01L27/1259
Abstract: The invention provides a method for manufacturing an array substrate which comprises a gate driving circuit including a plurality of thin film transistors and connection gate lines each connected between gates of two adjacent thin film transistors, the method comprises steps of: step S1, forming a pattern including the gates of the thin film transistors and the connection gate lines on a base; step S2, forming a gate insulation layer above the pattern including the gates of the thin film transistors and the connection gate lines; step S3, forming a pattern including a gate line protecting layer on the gate insulation layer, wherein the gate line protecting layer is above the connection gate lines; and step S4, forming a pattern including the sources and drains of the thin film transistors. The invention also provides an array substrate which is manufactured by above method, and a display device comprising the same.
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公开(公告)号：US09806109B2
公开(公告)日：2017-10-31
申请号：US14490814
申请日：2014-09-19
Inventor： Tiansheng Li , Zhenyu Xie
IPC: H01L27/14 , H01L27/12 , H01L21/027 , H01L21/3213 , G03F1/00
CPC classification number: H01L27/1288 , G03F1/00 , H01L21/0274 , H01L21/32139
Abstract: The present disclosure provides a half tone mask plate used to manufacture an active layer pattern as well as a source electrode pattern, a drain electrode pattern and a data line pattern located on the active layer pattern included in the array substrate. A surface of the array substrate includes a first region corresponding to the source electrode pattern, the drain electrode pattern and the data line pattern, a second region corresponding to a region of the active layer pattern located between the source electrode pattern and the drain electrode pattern, as well as a third region in addition to the first region and the second region; the half tone mask plate includes a semi-transparent region corresponding to the second region and a partial region of the third region.
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公开(公告)号：US09627543B2
公开(公告)日：2017-04-18
申请号：US14527893
申请日：2014-10-30
Inventor： Zhenyu Xie
IPC: H01L29/786 , H01L29/66 , H01L21/265 , H01L21/321
CPC classification number: H01L29/78675 , H01L21/26513 , H01L21/32105 , H01L29/66757 , H01L29/78609 , H01L29/78621
Abstract: The present disclosure provides a TFT, a method for manufacturing the same, an array substrate and a display device, so as to effectively reduce a TFT edge leakage current IOFF (edge). The TFT includes an active layer and a silicon oxide layer arranged at a lateral side of the active layer.
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14.发明授权Thin film transistor array substrate, manufacturing method thereof, and display device 有权薄膜晶体管阵列基板及其制造方法以及显示装置公开(公告)号：US09530807B2
公开(公告)日：2016-12-27
申请号：US13993666
申请日：2012-12-10
Inventor： Tiansheng Li , Wenyu Zhang , Zhenyu Xie
IPC: H01L27/12 , H01L29/786 , H01L33/36 , G02F1/1343 , G02F1/1337
CPC classification number: H01L27/1288 , G02F1/133707 , G02F1/134363 , G02F2001/134318 , H01L27/124 , H01L29/786 , H01L33/36
Abstract: A thin film transistor (TFT) array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method comprises: forming a first passivation layer (8) on a substrate (1), and forming a board wiring PAD-region via hole (11) in the first passivation layer (8) above the board wiring PAD region (11) through a first patterning process; forming a second passivation layer (16) on the substrate (1) formed with the board wiring PAD-region via hole (11), and forming a pixel-region via hole (15) in the first passivation layer (8) and the second passivation layer (16) above the display electrode (7) through a second patterning process in such a way that the pixel-region via hole (15) has a top-size smaller than its bottom-size; and applying a transparent conductive layer on the substrate (1) formed with the pixel-region via hole (15) to form a second display electrode.
Abstract translation: 提供薄膜晶体管（TFT）阵列基板，其制造方法和显示装置。 该制造方法包括：在基板（1）上形成第一钝化层（8），并且在板布线PAD区域（11）上方的第一钝化层（8）中形成板布线PAD区域通孔（11） 通过第一图案化过程; 在形成有所述基板配线PAD区域通孔（11）的基板（1）上形成第二钝化层（16），并且在所述第一钝化层（8）中形成像素区域通孔（15） 通过第二图案化工艺使显示电极（7）上方的钝化层（16）以像素区域通孔（15）的顶端尺寸小于其底部尺寸; 以及在形成有像素区域通孔（15）的衬底（1）上施加透明导电层以形成第二显示电极。
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公开(公告)号：US09437742B2
公开(公告)日：2016-09-06
申请号：US14348802
申请日：2013-09-27
Inventor： ChangJiang Yan , Jun Long , Xiaohui Zhu , Zhenyu Xie , Xu Chen
IPC: H01L29/786 , H01L23/535 , H01L29/66 , H01L27/12
CPC classification number: H01L29/78618 , H01L23/535 , H01L27/1225 , H01L29/66969 , H01L29/7869 , H01L29/78693 , H01L2924/0002 , H01L2924/00
Abstract: A thin film transistor, a manufacturing method thereof and an array substrate are provided. The thin film transistor includes: a gate electrode (102) formed on a substrate (101), a gate insulating layer (103) formed on the gate electrode (102) and covering at least a part of the substrate (101), and a semiconductor layer (105′), a source electrode (107a) and a drain electrode (107b) which are formed on the gate insulating layer (103). The material of the semiconductor layer (105′) is an oxide semiconductor; and the material of the source electrode (107a) and drain electrode (107b) is the oxide semiconductor which is doped. The source electrode (107a), the drain electrode (107b) and the semiconductor layer (105′) are disposed in the same layer.
Abstract translation: 提供薄膜晶体管，其制造方法和阵列基板。 薄膜晶体管包括：形成在基板（101）上的栅电极（102），形成在栅电极（102）上并覆盖基板（101）的至少一部分的栅极绝缘层（103） 形成在栅极绝缘层（103）上的半导体层（105'），源电极（107a）和漏电极（107b）。 半导体层（105'）的材料是氧化物半导体; 并且源电极（107a）和漏电极（107b）的材料是掺杂的氧化物半导体。 源电极（107a），漏电极（107b）和半导体层（105'）设置在同一层中。
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Patent Agency Ranking
公开(公告)号：US09343488B2
公开(公告)日：2016-05-17
申请号：US14133768
申请日：2013-12-19
Inventor： Zhenyu Xie
IPC: H01L21/336 , H01L21/28 , H01L27/12
CPC classification number: H01L27/1288
Abstract: According to embodiments of the invention, there are provided a TFT array substrate, a manufacturing method thereof and a liquid crystal display. The manufacturing method comprises manufacturing a pattern including a gate electrode, a gate insulating layer pattern with a via hole, a pattern including an active layer, a pattern including source and drain electrodes and a pattern including a first electrode on a substrate. The formation of the gate insulating layer pattern with the via hole and the pattern including the active layer are completed through one patterning process, the pattern including the gate electrode at least includes the gate electrode and a gate leading wire, the via hole of the gate insulating layer is located over the gate leading wire, and the active layer is located over the gate electrode.
Abstract translation: 根据本发明的实施例，提供了TFT阵列基板，其制造方法和液晶显示器。 该制造方法包括制造包括栅电极，具有通孔的栅绝缘层图案，包括有源层的图案，包括源电极和漏电极的图案以及在基板上包括第一电极的图案的图案。 通过一个图案化工艺完成具有通孔和栅极绝缘层图案的形成，包括有源层的图案，包括栅电极的图案至少包括栅电极和栅引线，栅极的通孔 绝缘层位于栅极引线上方，有源层位于栅极上方。
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公开(公告)号：US09236518B2
公开(公告)日：2016-01-12
申请号：US14128833
申请日：2012-12-03
Inventor： Changjiang Yan , Zhenyu Xie , Shaoying Xu , Tiansheng Li
IPC: H01L29/04 , H01L31/105 , H01L27/146 , H01L27/12 , H01L29/66 , H01L29/786 , H01L31/0256
CPC classification number: H01L31/1055 , H01L27/1214 , H01L27/14603 , H01L27/14616 , H01L27/14632 , H01L27/14687 , H01L27/14689 , H01L27/14692 , H01L29/66765 , H01L29/78669 , H01L31/0256
Abstract: A sensor and its fabrication method are provided, the sensor includes: a base substrate, a group of gate lines and a group of data lines arranged as crossing each other, and a plurality of sensing elements arranged in an array and defined by the group of gate lines and the group of data lines, each sensing element including a TFT device and a photodiode sensing device, wherein a channel region of the TFT device is inverted and the source and drain electrodes are positioned between the active layer and the gate electrode. The sensor reduces the number of mask as well as the production cost and simplifies the production process, thereby significantly improves the production capacity and the defect-free rate.
Abstract translation: 提供了一种传感器及其制造方法，该传感器包括：基底基板，一组栅极线和一组布置为彼此交叉的数据线;以及多个感测元件，其排列成阵列并由 栅极线和数据线组，每个感测元件包括TFT器件和光电二极管感测器件，其中TFT器件的沟道区域被反转，并且源极和漏极电极位于有源层和栅电极之间。 该传感器减少了掩模的数量和生产成本，简化了生产过程，从而显着提高了生产能力和无缺陷率。
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公开(公告)号：US20150179689A1
公开(公告)日：2015-06-25
申请号：US14356004
申请日：2013-06-20
Inventor： Zhenyu Xie , Shaoying Xu , Tiansheng Li , Changjiang Yan
IPC: H01L27/144 , H01L31/0203 , H01L31/20 , H01L31/0216
CPC classification number: H01L27/1443 , G02F1/13318 , G02F1/133512 , G02F2001/133388 , H01L27/1446 , H01L29/78633 , H01L29/78678 , H01L31/0203 , H01L31/02164 , H01L31/202
Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a display area and a non-display area. The non-display area includes at least one light sensor each including a light blocking layer on a substrate and for blocking light emitted from a backlight source; an insulating layer on the light blocking layer; a amorphous silicon layer on the insulating layer at a location corresponding to the light blocking layer and for sensing external light; an input electrode and an output electrode on the amorphous silicon layer and not contacting each other. The input electrode and the output electrode both contact the amorphous silicon layer, a part of the amorphous silicon layer between the input electrode and the output electrode forms a conductive channel. The output electrode is connected with a photoelectric detection circuit for inputting drain current generated by the conductive channel into the photoelectric detection circuit.
Abstract translation: 提供阵列基板，其制造方法和显示装置。 阵列基板包括显示区域和非显示区域。 非显示区域包括至少一个光传感器，每个光传感器包括在基板上的遮光层，并用于阻挡从背光源发射的光; 遮光层上的绝缘层; 在对应于遮光层的位置处的绝缘层上的非晶硅层，用于感测外部光; 非晶硅层上的输入电极和输出电极，并且彼此不接触。 输入电极和输出电极均接触非晶硅层，在输入电极和输出电极之间的非晶硅层的一部分形成导电通道。 输出电极与光电检测电路连接，用于将由导电通道产生的漏极电流输入光电检测电路。
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公开(公告)号：US09048161B2
公开(公告)日：2015-06-02
申请号：US14127353
申请日：2012-11-16
Inventor： Shaoying Xu , Zhenyu Xie , Xu Chen
IPC: H01L21/00 , H01L27/146
CPC classification number: H01L27/14683 , H01L27/14632 , H01L27/14658 , H01L27/14676 , H01L27/14687 , H01L27/14692
Abstract: A method for fabricating a sensor includes: forming, on a base substrate, a pattern of a source electrode and a drain electrode, a pattern of a data line, a pattern of a receiving electrode, a pattern of a photodiode, and a pattern of a transparent electrode disposed by using a first patterning process; forming a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer by using a third patterning process; forming a pattern of a gate insulating layer by using a fourth patterning process, wherein the gate insulating layer has a via hole above the transparent electrode; and forming a pattern of a gate electrode, a pattern of a gate line, and a pattern of a bias line connected to the transparent electrode via the via hole above the transparent electrode by using a fifth patterning process.
Abstract translation: 一种用于制造传感器的方法，包括：在基底基板上形成源电极和漏极的图案，数据线的图案，接收电极的图案，光电二极管的图案和图案 通过使用第一图案化工艺设置的透明电极; 通过使用第二图案化工艺形成欧姆层的图案; 通过使用第三图案化工艺形成有源层的图案; 通过使用第四图案化工艺形成栅极绝缘层的图案，其中所述栅极绝缘层在所述透明电极上方具有通孔; 以及通过使用第五图案化工艺，通过透明电极上方的通孔形成栅电极的图案，栅线的图案和与透明电极连接的图案的图案。
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公开(公告)号：US08951822B2
公开(公告)日：2015-02-10
申请号：US14127353
申请日：2012-11-16
Inventor： Shaoying Xu , Zhenyu Xie , Xu Chen
IPC: H01L21/00 , H01L27/146
Abstract: A method for fabricating a sensor includes: forming, on a base substrate, a pattern of a source electrode and a drain electrode, a pattern of a data line, a pattern of a receiving electrode, a pattern of a photodiode, and a pattern of a transparent electrode disposed by using a first patterning process; forming a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer by using a third patterning process; forming a pattern of a gate insulating layer by using a fourth patterning process, wherein the gate insulating layer has a via hole above the transparent electrode; and forming a pattern of a gate electrode, a pattern of a gate line, and a pattern of a bias line connected to the transparent electrode via the via hole above the transparent electrode by using a fifth patterning process.
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