公开(公告)号：US20060223247A1

公开(公告)日：2006-10-05

申请号：US11387603

申请日：2006-03-22

Applicant: Yanjun Ma ,  Ronald Oliver ,  Todd Humes ,  Jaideep Mavoori

Inventor： Yanjun Ma ,  Ronald Oliver ,  Todd Humes ,  Jaideep Mavoori

IPC: H01L21/338

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66143

Abstract: A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.

Abstract translation: 具有改进性能的肖特基结二极管器件是在常规CMOS工艺中制造的。 形成包括掺杂到第一导电类型的材料的衬底。 第一阱设置在衬底上。 第一阱包括掺杂到与第一导电类型相反的第二导电类型的材料。 含金属材料的区域设置在第一阱之上，以在含金属材料区域和第一阱之间的界面处形成肖特基结。 在一个实施例中，第一井接触设置在第一井的一部分中。 第二阱设置在衬底上，其中第二阱包括掺杂到第一导电类型的材料。 在一个实施例中，第一井和第二井不彼此直接接触。

公开(公告)号：US06407435B1

公开(公告)日：2002-06-18

申请号：US09502420

申请日：2000-02-11

Applicant: Yanjun Ma ,  Yoshi Ono

Inventor： Yanjun Ma ,  Yoshi Ono

IPC: H01L2976

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583

Abstract: A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Abstract translation: 提供了具有高k材料和插入材料的交替层的多层电介质叠层。 插入材料的存在和高k材料层的薄度降低或消除了高k材料内的结晶效应，即使在较高的退火温度下也是如此。 高k电介质层是优选锆或铪的金属氧化物。 插层优选为无定形氧化铝，氮化铝或氮化硅。 因为这些层减少了单个层内晶体结构的影响，所以整个隧穿电流降低。 还提供了作为沉积用于形成上述多层电介质叠层的所需材料的方法的原子层沉积，溅射和蒸发。

公开(公告)号：US06297539B1

公开(公告)日：2001-10-02

申请号：US09611356

申请日：2000-07-06

Applicant: Yanjun Ma ,  Yoshi Ono

Inventor： Yanjun Ma ,  Yoshi Ono

IPC: H01L2976

CPC classification number: H01L21/28185 ,  C23C14/083 ,  C23C16/405 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517

Abstract: A high-k dielectric films is provided, which is doped with divalent or trivalent metals to vary the electron affinity, and consequently the electron and hole barrier height. The high-k dielectric film is a metal oxide of either zirconium (Zr) or hafnium (Hf), doped with a divalent metal, such as calcium (Ca) or strontium (Sr), or a trivalent metal, such as aluminum (Al), scandium (Sc), lanthanum (La), or yttrium (Y). By selecting either a divalent or trivalent doping metal, the electron affinity of the dielectric material can be controlled, while also providing a higher dielectric constant material then silicon dioxide. Preferably, the dielectric material will also be amorphous to reduce leakage caused by grain boundaries. Also provided are sputtering, CVD, Atomic Layer CVD, and evaporation deposition methods for the above-mentioned, doped high dielectric films.

Abstract translation: 提供了高k电介质膜，其掺杂有二价或三价金属以改变电子亲和力，从而电子和空穴势垒高度。 高k电介质膜是掺杂有二价金属如钙（Ca）或锶（Sr）的锆（Zr）或铪（Hf）的金属氧化物，或三价金属如铝（Al ），钪（Sc），镧（La）或钇（Y）。 通过选择二价或三价掺杂金属，可以控制介电材料的电子亲和力，同时还提供较高的介电常数材料，然后是二氧化硅。 优选地，电介质材料也将是非晶体的，以减少由晶界引起的泄漏。 还提供了用于上述掺杂的高介电膜的溅射，CVD，原子层CVD和蒸发沉积方法。

公开(公告)号：US08349676B2

公开(公告)日：2013-01-08

申请号：US13214044

申请日：2011-08-19

Applicant: Cong Khieu ,  Yanjun Ma ,  Jaideep Mavoori

Inventor： Cong Khieu ,  Yanjun Ma ,  Jaideep Mavoori

IPC: H01L21/337

CPC classification number: H01L27/0251

Abstract: Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 装置，系统和方法可以包括通过使用具有非对准栅极的半导体器件来管理静电放电事件以实现快速反向电压保护机制。 这样的器件可以通过掺杂半导体衬底以形成阱中的第一导电区域形成，形成阱中的源极区域和漏极区域之一，在衬底上沉积多晶硅层以建立栅极区域 与源极区域和漏极区域中的一个重叠，并且形成由衬底支撑的集成电路以耦合到源极区域和漏极区域中的一个，以在集成电路和漏极区域之间的节点处提供快速恢复电压操作 源极或漏极区。 公开了附加装置，系统和方法。

公开(公告)号：US08188927B1

公开(公告)日：2012-05-29

申请号：US12399913

申请日：2009-03-06

Applicant: Ronald Lee Koepp ,  Ronald A. Oliver ,  William T. Colleran ,  Yanjun Ma ,  Jay M. Fassett ,  Vincent C. Moretti

Inventor： Ronald Lee Koepp ,  Ronald A. Oliver ,  William T. Colleran ,  Yanjun Ma ,  Jay M. Fassett ,  Vincent C. Moretti

IPC: H01Q1/38

CPC classification number: H01Q23/00 ,  G06K19/07756 ,  H01Q1/2208

Abstract: RFID tags are assembled through affixing an antenna to an integrated circuit (IC) by forming one or more capacitors coupling the antenna and the IC with the dielectric material of the capacitor(s) including a non-conductive covering layer of the IC, a non-conductive covering layer of the antenna such as an oxide layer, and/or an additionally formed dielectric layer. Top and bottom plates of the capacitor(s) are formed by the antenna traces and one or more patches on a top surface of the IC.

Abstract translation: RFID标签通过将天线和IC的电容器与电容器的电介质材料形成一个或多个电容器组成，该电容器包括IC的非导电覆盖层，非集成电路 天线的导电覆盖层，例如氧化物层，和/或另外形成的电介质层。 电容器的顶板和底板由天线迹线和IC顶表面上的一个或多个贴片形成。

公开(公告)号：US20120016657A1

公开(公告)日：2012-01-19

申请号：US13182281

申请日：2011-07-13

Applicant: Yifan He ,  Yanjun Ma ,  Andrew Way ,  Josef van Genabith

Inventor： Yifan He ,  Yanjun Ma ,  Andrew Way ,  Josef van Genabith

IPC: G06F17/28

CPC classification number: G06F17/2836

Abstract: A translation system for translating source text from a first language to target text in a second language. The system comprises a translation memory (TM) module that stores translation segments. The TM module is operable to generate a TM target text output in response to source text. A statistical translation machine (SMT) module is configured to generate translations on the basis of statistical models whose parameters are derived from the analysis of bilingual text corpora. The SMT module is operable to generate a SMT target text output in response to source text. An extractor is configured to extract features from the TM target text output and the SMT target text output. A vector generator is configured to generate a vector with a unified feature set derived from the extracted features and features associated with the SMT module and the TM module. A recommender is operable to read the vector and determine whether the TM target text output or the SMT target text output is optimum for post editing.

Abstract translation: 用于将源文本从第一语言翻译成以第二语言定向文本的翻译系统。 该系统包括存储翻译段的翻译记忆（TM）模块。 TM模块可操作以响应于源文本生成TM目标文本输出。 统计翻译机（SMT）模块被配置为基于其参数来自双语文本语料库的分析的统计模型生成翻译。 SMT模块可操作以响应于源文本生成SMT目标文本输出。 提取器被配置为从TM目标文本输出和SMT目标文本输出中提取特征。 向量生成器被配置为生成具有从提取的特征和与SMT模块和TM模块相关联的特征导出的统一特征集的向量。 推荐器可操作以读取该矢量并确定TM目标文本输出或SMT目标文本输出是否适于后期编辑。

公开(公告)号：US20110147469A1

公开(公告)日：2011-06-23

申请号：US13034608

申请日：2011-02-24

Applicant: Yanjun Ma ,  Steven I. Mozsgai

Inventor： Yanjun Ma ,  Steven I. Mozsgai

IPC: G06K19/073 ,  G11C16/04

CPC classification number: G11C16/0433 ,  G11C16/20 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11531 ,  H01L27/11534 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.

Abstract translation: 提供了一种非易失性存储器（NVM）电路，其包括至少第一和第二NVM子阵列。 第一个子阵列是从第一个存储单元构建的。 第二NVM子阵列由与第一存储器单元不同的构造的第二存储器单元构建。 NVM子阵列共享支持电路。 在一些实施例中，可以构造子阵列，使得它们具有根据其预期用途定制的不同特征。 例如，一个子阵列可能被定制用于数据保留，而用于编程耐久性的下一个子阵列，还是另一个用于写干扰抗扰度的子阵列。

公开(公告)号：US20060223246A1

公开(公告)日：2006-10-05

申请号：US11387515

申请日：2006-03-22

Applicant: Yanjun Ma ,  Ronald Oliver ,  Todd Humes ,  Jaideep Mavoori

Inventor： Yanjun Ma ,  Ronald Oliver ,  Todd Humes ,  Jaideep Mavoori

IPC: H01L21/338

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66143

Abstract: A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.

Abstract translation: 在传统的CMOS工艺中制造了具有改进的性能和多阱结构的肖特基结二极管器件。 形成包括掺杂到第一导电类型的材料的衬底。 第一阱设置在衬底上。 第一阱包括不同掺杂的材料，例如与第一导电类型相反的第二导电类型。 第二口井设置在第一井内。 含金属材料的区域设置在第二阱中以在含金属材料区域和第二阱之间的界面处形成肖特基结。 在一个实施例中，第二井接触设置在第二井的一部分中。

公开(公告)号：US06716645B2

公开(公告)日：2004-04-06

申请号：US10319314

申请日：2002-12-12

Applicant: Tingkai Li ,  Sheng Teng Hsu ,  Hong Ying ,  Bruce D. Ulrich ,  Yanjun Ma

Inventor： Tingkai Li ,  Sheng Teng Hsu ,  Hong Ying ,  Bruce D. Ulrich ,  Yanjun Ma

IPC: H01L2100

CPC classification number: H01L21/28291 ,  H01L29/516 ,  H01L29/78391

Abstract: A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.

Abstract translation: 用于铁电非易失性存储器件的MFMOS单晶体管存储器结构包括诸如ZrO 2，HfO 2，Y 2 O 3或La 2 O 3等的高介电常数材料或其混合物，以减少操作电压并增加存储窗口， 设备的可靠性。

公开(公告)号：US06627503B2

公开(公告)日：2003-09-30

申请号：US10137567

申请日：2002-04-30

Applicant: Yanjun Ma ,  Yoshi Ono

Inventor： Yanjun Ma ,  Yoshi Ono

IPC: H01L21336

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583

Abstract: A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.