公开(公告)号：US5510295A

公开(公告)日：1996-04-23

申请号：US145921

申请日：1993-10-29

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Francois M. d'Heurle ,  James M. E. Harper ,  Randy W. Mann ,  Glen L. Miles ,  Donald W. D. Rakowski

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Francois M. d'Heurle ,  James M. E. Harper ,  Randy W. Mann ,  Glen L. Miles ,  Donald W. D. Rakowski

IPC分类号： C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44

CPC分类号： C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665 ,  Y10S148/04 ,  Y10S148/147

摘要： The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10.sup.17 atoms/cm.sup.3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700.degree. C., and more preferably between about 600.degree.-700.degree. C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900.degree. C.

摘要翻译： 形成在半导体晶片上的硅层上形成的金属硅化物层的相变温度降低。 首先，将难熔金属设置在硅层的表面附近，在覆盖难熔金属的层中沉积前体金属，并将晶片加热到足以从前体金属形成金属硅化物的温度。 前体金属可以是难熔金属，优选为钛，钨或钴。 硅层表面的难熔金属的浓度优选小于约1017原子/ cm3。 难熔金属可以是Mo，Co，W，Ta，Nb，Ru或Cr，更优选为Mo或Co。用于形成硅化物的加热步骤在低于约700℃的温度下进行， 更优选在约600℃至700℃之间。任选地，在沉积难熔金属的步骤之后，并且在沉积前体金属层的步骤之前，将晶片退火。 优选地，该退火步骤在至少约900℃的晶片温度下进行。

公开(公告)号：US08597994B2

公开(公告)日：2013-12-03

申请号：US13113901

申请日：2011-05-23

申请人： Randy W. Mann

发明人： Randy W. Mann

IPC分类号： H01L21/8238

CPC分类号： H01L27/1211 ,  G11C11/412 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1104

摘要： A semiconductor device is provided that includes a first inverter having a first p-channel FinFET and a first n-channel FinFET each coupled to a first shared contact forming a first cell node and having a first common gate. A second inverter is included having a second p-channel FinFET and a second n-channel FINFET each coupled to a second shared contact forming a second cell node and having a second common gate aligned with the first shared contact of the first inverter forming a latch circuit. Additionally, a pair of FinFET passgates are included each having a drain contact respectively coupled the first and second cell nodes and a source contact connected to one of a complementary bit line. Finally, a word line is connected to a gate contact of each of the pair of FinFET passgates to provide a static random access memory cell.

摘要翻译： 提供了一种半导体器件，其包括具有第一p沟道FinFET和第一n沟道FinFET的第一反相器，每个第一反相器耦合到形成第一单元节点并具有第一公共栅极的第一共享触点。 第二反相器包括具有第二p沟道FinFET和第二n沟道FINFET，每个第二p沟道FinFET和第二n沟道FINFET耦合到形成第二单元节点的第二共享触点，并且具有与形成锁存器的第一反相器的第一共享触点对准的第二公共栅极 电路。 此外，包括一对FinFET传递门，每一个具有分别耦合第一和第二单元节点的漏极触点和连接到互补位线之一的源极触点。 最后，字线连接到一对FinFET传递门中的每一个的栅极触点，以提供静态随机存取存储单元。

公开(公告)号：US08563398B2

公开(公告)日：2013-10-22

申请号：US12977134

申请日：2010-12-23

申请人： Gregory Costrini ,  Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Randy W. Mann

发明人： Gregory Costrini ,  Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Randy W. Mann

IPC分类号： H01L21/30

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1203

摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.

摘要翻译： 公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。 在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。 导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

公开(公告)号：US07923840B2

公开(公告)日：2011-04-12

申请号：US11621699

申请日：2007-01-10

申请人： Gregory Costrini ,  Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Randy W. Mann

发明人： Gregory Costrini ,  Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Randy W. Mann

IPC分类号： H01L23/48

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1203

摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.

摘要翻译： 公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。 在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。 导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

公开(公告)号：US07390721B2

公开(公告)日：2008-06-24

申请号：US11231385

申请日：2005-09-21

申请人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

发明人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

公开(公告)号：US07057180B2

公开(公告)日：2006-06-06

申请号：US10604416

申请日：2003-07-18

申请人： John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Jeffery H. Oppold ,  Norman J. Rohrer

发明人： John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Jeffery H. Oppold ,  Norman J. Rohrer

IPC分类号： G01T1/24

CPC分类号： G11C11/4125

摘要： A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.

摘要翻译： 一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。 本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。 冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。 如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。 检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。 检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。 在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。 检测电路的第二个应用是传统的逻辑电路。

公开(公告)号：US06900505B2

公开(公告)日：2005-05-31

申请号：US10709174

申请日：2004-04-19

申请人： Jonanthan D. Chapple-Sokol ,  Randy W. Mann ,  William J. Murphy ,  Jed H. Rankin ,  Daniel S. Vanslette

发明人： Jonanthan D. Chapple-Sokol ,  Randy W. Mann ,  William J. Murphy ,  Jed H. Rankin ,  Daniel S. Vanslette

IPC分类号： C23C28/00 ,  H01L31/119

CPC分类号： C23C28/00 ,  Y10T428/12

摘要： A structure which ensures against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 Å, serves a sacrificial purpose and prevents damage to an underlying silicide layer by blocking interaction between any fluorine and the underlying silicide that is released when the refractory material is formed.

摘要翻译： 通过首先在耐火材料沉积之前提供连续的多晶硅层，来实现通过物理气相沉积（PVD）或化学气相沉积（CVD）来确保防止耐火材料层沉积下层硅化物层的劣化的结构。 连续多晶硅层优选不大于50，用于牺牲目的，并且通过阻止在形成耐火材料时释放的任何氟和下面的硅化物之间的相互作用来防止对下面的硅化物层的损伤。

公开(公告)号：US06891419B2

公开(公告)日：2005-05-10

申请号：US10604554

申请日：2003-07-30

申请人： Paul D. Kartschoke ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Norman J. Rohrer

发明人： Paul D. Kartschoke ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Norman J. Rohrer

IPC分类号： H03K3/037 ,  H03K3/356

CPC分类号： H03K3/356104 ,  H03K3/0375

摘要： In a first aspect, a cross-coupled inverter is provided that includes a first inverter circuit having a first NFET coupled to a first PFET and a second inverter circuit having a second NFET coupled to a second PFET. The second inverter circuit is cross-coupled with the first inverter circuit at a plurality of nodes. The body of at least one of the first NFET, the second NFET, the first PFET and the second PFET is coupled so as to form a feedback path that reduces discharging at one or more of the plurality of nodes in response to a soft error event at the cross-coupled inverter.

摘要翻译： 在第一方面，提供一种交叉耦合的反相器，其包括具有耦合到第一PFET的第一NFET的第一反相器电路和具有耦合到第二PFET的第二NFET的第二反相器电路。 第二逆变器电路在多个节点处与第一反相器电路交叉耦合。 第一NFET，第二NFET，第一PFET和第二PFET中的至少一个的主体被耦合以形成反馈路径，其减少响应于软错误事件的多个节点中的一个或多个的放电 在交叉耦合的逆变器。

公开(公告)号：US06700163B2

公开(公告)日：2004-03-02

申请号：US09683278

申请日：2001-12-07

申请人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

发明人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

IPC分类号： H01L2976

CPC分类号： H01L21/823871 ,  H01L21/823842

摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

摘要翻译： 本文公开了选择性硅化半导体结构及其制造方法。 半导体结构在N +扩散或N +有源区域之间的多晶硅线路上存在自杀，并且在多晶硅线路的N + / P +结处的P +扩散或有源区域存在自杀，并且在N +有源区域和P +活性区域上不存在硅化物 区。 这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。 在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

公开(公告)号：US06624475B2

公开(公告)日：2003-09-23

申请号：US09996413

申请日：2001-11-29

申请人： Andres Bryant ,  Randy W. Mann ,  Anthony K. Stamper

发明人： Andres Bryant ,  Randy W. Mann ,  Anthony K. Stamper

IPC分类号： H01L2701

CPC分类号： H01L29/66757 ,  H01L29/78615

摘要： An FET device and method of making comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a second conductivity type formed in the substrate layer, the diffusion regions each having edges, the edges of the FET diffusion regions being separated by the channel region; and a body contact region of the first conductivity type extending continuously from the channel region. The first conductivity type material in the body contact region is thinner than the first conductivity type material in the channel region. The FET also includes a second dielectric layer formed on the body contact region.