公开(公告)号：US20070111419A1

公开(公告)日：2007-05-17

申请号：US11649545

申请日：2007-01-03

申请人： Brian Doyle ,  Been-Yin Jin ,  Jack Kavalieros ,  Suman Datta ,  Justin Brask ,  Robert Chau

发明人： Brian Doyle ,  Been-Yin Jin ,  Jack Kavalieros ,  Suman Datta ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/8234 ,  H01L29/74

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

公开(公告)号：US20070001219A1

公开(公告)日：2007-01-04

申请号：US11173866

申请日：2005-06-30

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Uday Shah ,  Suman Datta ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Uday Shah ,  Suman Datta ,  Robert Chau

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858

摘要： A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

摘要翻译： 一种用于纳米尺度通道器件的接触结构，其具有耦合到具有多个平行半导体器件的器件的源极或漏极区域之间并具有接触结构的接触结构。 接触结构能够接触具有亚光刻间距的平行半导体本体。

公开(公告)号：US20060237801A1

公开(公告)日：2006-10-26

申请号：US11110485

申请日：2005-04-20

申请人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Brian Doyle ,  Robert Chau

发明人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L29/15

CPC分类号： H01L29/4966 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7849

摘要： Strained channel field effect transistors may have a threshold voltage shift. This threshold voltage shift may be compensated for by adjusting channel doping. But this also adversely affects mobility. The threshold voltage shift may be compensated, without adversely affecting mobility, by tailoring the workfunction of a metal gate electrode used in the transistor to adequately compensate for that threshold voltage shift. For example, in some embodiments, an appropriate metal may be selected with a slightly higher workfunction or, in other cases, the workfunction of a selected metal may be adjusted by, for example, doping the metal gate electrode with a material which increases the workfunction of the gate electrode.

摘要翻译： 应变通道场效应晶体管可具有阈值电压偏移。 该阈值电压偏移可以通过调整沟道掺杂来补偿。 但这也对行动不利。 可以通过调整在晶体管中使用的金属栅电极的功函数来充分补偿该阈值电压偏移来补偿阈值电压偏移而不会不利地影响迁移率。 例如，在一些实施例中，可以选择具有略高的功函数的合适的金属，或者在其他情况下，可以通过例如用增加功函数的材料掺杂金属栅电极来调整所选金属的功函数 的栅电极。

公开(公告)号：US20060228840A1

公开(公告)日：2006-10-12

申请号：US11297084

申请日：2005-12-07

申请人： Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott Hareland

发明人： Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott Hareland

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

公开(公告)号：US20060220074A1

公开(公告)日：2006-10-05

申请号：US11096984

申请日：2005-03-31

申请人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

发明人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

摘要： A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

摘要翻译： 描述了在碳纳米管内形成能量阱的结构。 该结构包括掺杂半导体区域和未掺杂的半导体区域。 碳纳米管位于掺杂半导体区域和未掺杂的半导体区域之间。 该结构还包括δ掺杂半导体区域。 未掺杂的半导体区域在碳纳米管和δ掺杂区之间。 该掺杂掺杂的δ掺杂半导体区域与掺杂半导体区域的掺杂相反。

公开(公告)号：US20060202266A1

公开(公告)日：2006-09-14

申请号：US11080765

申请日：2005-03-14

申请人： Marko Radosavljevic ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Amian Majumdar ,  Robert Chau

发明人： Marko Radosavljevic ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Amian Majumdar ,  Robert Chau

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/41791 ,  H01L21/3141 ,  H01L23/485 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/78621 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

摘要翻译： 一种半导体器件，包括形成在形成在半导体膜上的栅极电介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上的沟道区域附近。 源极和漏极区域各自包括与半导体沟道相邻并与其接触的半导体部分和与半导体部分相邻并与其接触的金属部分。

公开(公告)号：US20060189156A1

公开(公告)日：2006-08-24

申请号：US11064648

申请日：2005-02-23

申请人： Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Matthew Metz ,  Suman Datta ,  Brian Doyle ,  Robert Chau

发明人： Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Matthew Metz ,  Suman Datta ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02244 ,  H01L21/02175 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31683 ,  H01L21/31691 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

摘要： A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer.

摘要翻译： 描述制造半导体器件的方法。 该方法包括形成接触金属氧化物层的高k栅介质层。 金属氧化物层通过形成金属层，然后氧化金属层而产生。

公开(公告)号：US20060071285A1

公开(公告)日：2006-04-06

申请号：US10953295

申请日：2004-09-29

申请人： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Brian Doyle

发明人： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Brian Doyle

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/28079 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

摘要： In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.

摘要翻译： 在金属栅极替换工艺中，可以在NMOS和PMOS晶体管的沟道中选择性地诱发应变。 例如，可以使用具有比衬底更高的热膨胀系数的材料来形成PMOS晶体管的栅电极。 可以使用具有比基板的热膨胀系数更低的热膨胀系数的材料来形成NMOS晶体管的栅电极。

公开(公告)号：US20060068591A1

公开(公告)日：2006-03-30

申请号：US11240440

申请日：2005-09-29

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian Doyle ,  Justin Brask ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian Doyle ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/302

CPC分类号： H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

摘要： A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

摘要翻译： 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许在沟道区下方除去氧化物。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。

公开(公告)号：US20050199950A1

公开(公告)日：2005-09-15

申请号：US11123565

申请日：2005-05-06

申请人： Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott Hareland

发明人： Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott Hareland

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.