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143 条记录 (耗时 0.037 秒)

    MEMORY DEVICE AND METHOD FOR SENSING AND FIXING MARGIN CELLS
    11.
    发明申请
    MEMORY DEVICE AND METHOD FOR SENSING AND FIXING MARGIN CELLS 有权
    用于感测和固定细胞的记忆装置和方法

    公开(公告)号：US20100321987A1

    公开(公告)日：2010-12-23

    申请号：US12488995

    申请日：2009-06-22

    申请人： Hsiang-Lan Lung ,  Yen-Hao Shih

    发明人： Hsiang-Lan Lung ,  Yen-Hao Shih

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C7/06

    CPC分类号： G11C13/004 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/3431 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

    摘要： A programmable resistance memory device with a margin cell detection and refresh resources. Margin cell detection and refresh can comprise reading a selected cell, measuring a time interval which correlates with resistance of the selected cell during said reading, and enabling a refresh process if the measured time falls within a pre-specified range. The refresh process includes determining a data value stored in the selected cell, using for example a destructive read process, and refreshing the data value in the selected cell. The time interval can be measured by detecting timing within the sensing interval of a transition of voltage or current on a bit line across a threshold.

    摘要翻译： 具有边缘单元检测和刷新资源的可编程电阻存储器件。 边缘小区检测和刷新可以包括读取所选择的小区，测量在所述读取期间与所选择的小区的电阻相关的时间间隔，以及如果所测量的时间落在预定的范围内，则启用刷新过程。 刷新过程包括使用例如破坏性读取处理确定存储在所选择的单元中的数据值，以及刷新所选择的单元中的数据值。 可以通过检测跨越阈值的位线上的电压或电流的转变的感测间隔内的定时来测量时间间隔。

    MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS
    12.
    发明申请
    MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS 有权
    具有多晶硅管和单晶半导体区域的PN结的存储器单元访问器件

    公开(公告)号：US20100117049A1

    公开(公告)日：2010-05-13

    申请号：US12267492

    申请日：2008-11-07

    申请人： HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    发明人： HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    IPC分类号： H01L47/00 ,  H01L21/36

    CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

    摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

    摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

    Dielectric charge trapping memory cells with redundancy
    15.
    发明授权
    Dielectric charge trapping memory cells with redundancy 有权
    介质电荷捕获具有冗余的存储单元

    公开(公告)号：US09019771B2

    公开(公告)日：2015-04-28

    申请号：US13661723

    申请日：2012-10-26

    申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

    发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

    IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/10

    CPC分类号： G11C16/0475 ,  G11C16/10

    摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.

    摘要翻译： 介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。 一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。 在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。 可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

    Phase change memory coding
    16.
    发明授权
    Phase change memory coding 有权
    相变存储器编码

    公开(公告)号：US08634235B2

    公开(公告)日：2014-01-21

    申请号：US12823508

    申请日：2010-06-25

    申请人： Hsiang-Lan Lung ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

    发明人： Hsiang-Lan Lung ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

    摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

    摘要翻译： 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

    3D memory array arranged for FN tunneling program and erase
    17.
    发明授权
    3D memory array arranged for FN tunneling program and erase 有权
    3D存储阵列用于FN隧道编程和擦除

    公开(公告)号：US08426294B2

    公开(公告)日：2013-04-23

    申请号：US13476964

    申请日：2012-05-21

    申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

    发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

    IPC分类号： H01L29/76

    CPC分类号： G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

    摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

    摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。