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292 条记录 (耗时 0.03 秒)

    Method and apparatus providing improved data path calibration for memory devices
    11.
    发明授权
    Method and apparatus providing improved data path calibration for memory devices 失效
    为存储器件提供改进的数据路径校准的方法和装置

    公开(公告)号：US06587804B1

    公开(公告)日：2003-07-01

    申请号：US09637088

    申请日：2000-08-14

    申请人： Brian Johnson ,  Brent Keeth

    发明人： Brian Johnson ,  Brent Keeth

    IPC分类号： G06F112

    CPC分类号： G11C29/028 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2254

    摘要： A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.

    摘要翻译： 用于校准数字电路的数据路径的方法和装置使用偶数位伪随机校准模式。 在捕获周期中捕获图案的一部分，并用于预测校准图案的下一个到达部分。 捕获校准图案的下一个到达部分，然后在比较周期中与预测图案进行比较，并将比较结果用于到数据路径中的相对时间数据到数据中的时钟信号。 可以改变比较周期的持续时间以确保在校准过程中使用校准图案的所有可能位。

    Memory system and method for strobing data, command and address signals
    13.
    发明授权
    Memory system and method for strobing data, command and address signals 有权

    公开(公告)号：US07269094B2

    公开(公告)日：2007-09-11

    申请号：US11352131

    申请日：2006-02-10

    申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

    发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

    IPC分类号： G11C8/00

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

    摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

    Memory system and method for strobing data, command and address signals
    18.
    发明申请
    Memory system and method for strobing data, command and address signals 有权

    公开(公告)号：US20060126406A1

    公开(公告)日：2006-06-15

    申请号：US11352142

    申请日：2006-02-10

    申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

    发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

    摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

    Multi-mode synchronous memory device and methods of operating and testing same
    20.
    发明授权
    Multi-mode synchronous memory device and methods of operating and testing same 失效

    公开(公告)号：US06842398B2

    公开(公告)日：2005-01-11

    申请号：US10703275

    申请日：2003-11-07

    申请人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    发明人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    IPC分类号： G01R31/28 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C8/00

    CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

    摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.