公开(公告)号：US20070205468A1

公开(公告)日：2007-09-06

申请号：US11746141

申请日：2007-05-09

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC分类号： H01L27/092

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

摘要翻译： CMOS集成电路包括具有带有P阱的NMOS区域和具有N阱的PMOS区域的衬底。 在NMOS和PMOS区之间形成浅沟槽隔离（STI）区，并且在所述P阱区和所述N阱区之上形成包含应变SiGe层的复合硅层。 复合硅层在STI区域断开。 然后在NMOS和PMOS区域中的复合层上形成栅电极。

公开(公告)号：US07238989B2

公开(公告)日：2007-07-03

申请号：US11201990

申请日：2005-08-11

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

IPC分类号： H01L27/01

CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203

摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

摘要翻译： 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

公开(公告)号：US20050272188A1

公开(公告)日：2005-12-08

申请号：US11201990

申请日：2005-08-11

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203

摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

摘要翻译： 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

公开(公告)号：US20050009263A1

公开(公告)日：2005-01-13

申请号：US10730778

申请日：2003-12-09

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Hu

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

公开(公告)号：US07659587B2

公开(公告)日：2010-02-09

申请号：US11746141

申请日：2007-05-09

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC分类号： H01L21/00

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

摘要翻译： CMOS集成电路包括具有带有P阱的NMOS区域和具有N阱的PMOS区域的衬底。 在NMOS和PMOS区之间形成浅沟槽隔离（STI）区，并且在所述P阱区和所述N阱区之上形成包含应变SiGe层的复合硅层。 复合硅层在STI区域断开。 然后在NMOS和PMOS区域中的复合层上形成栅电极。

公开(公告)号：US07226832B2

公开(公告)日：2007-06-05

申请号：US11227264

申请日：2005-09-15

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC分类号： H01L21/8238

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

摘要翻译： CMOS集成电路包括具有带有P阱的NMOS区域和具有N阱的PMOS区域的衬底。 在NMOS和PMOS区之间形成浅沟槽隔离（STI）区，并且在所述P阱区和所述N阱区之上形成包含应变SiGe层的复合硅层。 复合硅层在STI区域断开。 然后在NMOS和PMOS区域中的复合层上形成栅电极。

公开(公告)号：USRE45180E1

公开(公告)日：2014-10-07

申请号：US12792373

申请日：2010-06-02

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L21/311 ,  H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/085 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

摘要翻译： 提供了一种用于形成半导体器件的方法和使用该方法制造的器件。 在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。 通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。 沟槽部分地填充有电介质材料。 去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。

公开(公告)号：USRE45165E1

公开(公告)日：2014-09-30

申请号：US13372622

申请日：2012-02-14

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yu Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yu Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L29/06 ,  H01L27/085 ,  H01L29/04

CPC分类号： H01L29/1079 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

公开(公告)号：US08618524B2

公开(公告)日：2013-12-31

申请号：US13029436

申请日：2011-02-17

申请人： Chun-Sheng Liang ,  Tzyh-Cheang Lee ,  Fu-Liang Yang

发明人： Chun-Sheng Liang ,  Tzyh-Cheang Lee ,  Fu-Liang Yang

IPC分类号： H01L45/00

CPC分类号： H01L45/12 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1683

摘要： A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.

摘要翻译： 存储器件包括相变元件，该相变元件还包括具有第一晶粒尺寸的第一相变层; 以及在所述第一相变层上的第二相变层。 第一和第二相变层是相变元件的深度区域。 第二相变层具有与第一平均晶粒尺寸不同的第二平均晶粒尺寸。

公开(公告)号：US08288842B2

公开(公告)日：2012-10-16

申请号：US11655008

申请日：2007-01-18

申请人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

发明人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L23/544 ,  H01L21/301

CPC分类号： H01L21/78 ,  B28D5/00

摘要： A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.

摘要翻译： 一种方法提供用具有金刚石结构的具有基底材料的晶片切割。 晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。 然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。 制造具有一个或多个模具的晶片，其上的至少一个边缘与形成晶片的基底材料的金刚石结构的天然裂解方向成偏移角。 至少一个切割线具有一个或多个保护元件，用于在晶片沿着切割线切割时保护模具不受不期望的开裂。