公开(公告)号：US06953972B2

公开(公告)日：2005-10-11

申请号：US10730778

申请日：2003-12-09

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/76

CPC classification number: H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

Abstract translation: 已经开发了用于制造具有包含应变SiGe层的沟道区的CMOS器件的工艺。 该工艺的特点是在N阱和P阱区的顶表面上复合硅层的选择性生长。 复合硅层由夹在选择性生长的未掺杂硅层之间的薄的应变SiGe层组成。 SiGe层中Ge的含量在约20至40重量％之间，允许存在增加的载流子迁移率而不产生硅缺陷。 薄的二氧化硅栅极绝缘体从选择性地生长的硅层的顶部热生长，位于覆盖选择性生长的SiGe层上。

公开(公告)号：US20050179076A1

公开(公告)日：2005-08-18

申请号：US11098112

申请日：2005-04-04

Applicant: Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

Inventor： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

IPC: H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Abstract translation: 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

公开(公告)号：US20050133817A1

公开(公告)日：2005-06-23

申请号：US10710012

申请日：2004-06-11

Applicant: Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/76

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66545 ,  Y10S438/933

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract translation: 一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分 覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

公开(公告)号：US20050051866A1

公开(公告)日：2005-03-10

申请号：US10798063

申请日：2004-03-11

Applicant: Howard Wang ,  Chenming Hu ,  Chun-Chieh Lin

Inventor： Howard Wang ,  Chenming Hu ,  Chun-Chieh Lin

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8239 ,  H01L29/06 ,  H01L31/0256

CPC classification number: H01L29/6656 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/1052

Abstract: A method is described for forming three or more spacer widths in transistor regions on a substrate. In one embodiment, different silicon nitride thicknesses are formed above gate electrodes followed by nitride etching to form spacers. Optionally, different gate electrode thicknesses may be fabricated and a conformal oxide layer is deposited which is subsequently etched to form different oxide spacer widths. A third embodiment involves a combination of different gate electrode thickness and different nitride thicknesses. A fourth embodiment involves selectively thinning an oxide layer over certain gate electrodes before etching to form spacers. Therefore, spacer widths can be independently optimized for different transistor regions on a substrate to enable better drive current in transistors with narrow spacers and improved SCE control in neighboring transistors with wider spacers. Better drive current is also obtained in transistors with shorter polysilicon thickness.

Abstract translation: 描述了用于在衬底上的晶体管区域中形成三个或更多个间隔物宽度的方法。 在一个实施例中，在栅电极之上形成不同的氮化硅厚度，随后氮化物蚀刻以形成间隔物。 可选地，可以制造不同的栅极电极厚度，并且沉积保形氧化物层，其随后被蚀刻以形成不同的氧化物间隔物宽度。 第三实施例涉及不同栅电极厚度和不同氮化物厚度的组合。 第四实施例涉及在蚀刻之前在某些栅电极上选择性地稀薄氧化物层以形成间隔物。 因此，可以对衬底上的不同晶体管区域独立地优化间隔物宽度，以在具有窄间隔物的晶体管中实现更好的驱动电流并且在具有较宽间隔物的相邻晶体管中改善SCE控制。 更薄的多晶硅厚度的晶体管也可获得更好的驱动电流。

公开(公告)号：US20050035409A1

公开(公告)日：2005-02-17

申请号：US10729095

申请日：2003-12-05

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/01 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Abstract translation: 半导体芯片包括其中设置有第一和第二有源区的半导体衬底126。 电阻器124形成在第一有源区域中，并且电阻器124包括形成在两个端子136之间的掺杂区域128.应变沟道晶体管132形成在第二有源区域中。 该晶体管包括第一和第二应力源141，该第一和第二应力器141形成在与基片相反的相邻的应变通道区域143之间。

公开(公告)号：US20120319278A1

公开(公告)日：2012-12-20

申请号：US13161701

申请日：2011-06-16

Applicant: Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

Inventor： Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括形成具有多个第一开口的图案化电介质层。 该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。 该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。 该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。 该方法包括去除沟槽掩模层。

公开(公告)号：US07705340B2

公开(公告)日：2010-04-27

申请号：US11163118

申请日：2005-10-05

Applicant: Chun-Chieh Lin

Inventor： Chun-Chieh Lin

IPC: H01L47/00

CPC classification number: H01L27/228 ,  H01L43/08

Abstract: Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.

Abstract translation: 本文公开了具有非平面形式的磁阻结构。 本发明的MR结构的实施例包括那些在MR结构的第一部分之间相对于衬底稍微垂直的第一部分和MR结构相对于衬底稍微水平的第二部分的至少一个拐点。 这种结构可以用于存储器件，例如MRAM存储器件，其中与具有先前的平面MR结构的器件相比，存储器密度增加而不减小MR结构的表面积。

公开(公告)号：US07656433B2

公开(公告)日：2010-02-02

申请号：US11707967

申请日：2007-02-20

Applicant: Chi-Hsien Wang ,  Wen-Ming Huang ,  Wei-Song Yeh ,  Chun-Chieh Lin ,  Kuan-Chou Chen

Inventor： Chi-Hsien Wang ,  Wen-Ming Huang ,  Wei-Song Yeh ,  Chun-Chieh Lin ,  Kuan-Chou Chen

IPC: H04N5/228 ,  H04N5/225 ,  H04N7/26

CPC classification number: H04N19/184 ,  H04N19/91

Abstract: A web camera includes an image sensor, which takes an external image; a sensor interface, which is connected to the mage sensor to receive and convert the image taken by the image sensor into digital image data; at least one compression module, which is connected to the sensor interface to receive and compress the digital image data into compressed image data; and a USB interface, which is connected to the compression module to output the compressed image data to a host device having a USB interface port, such as a computer and a USB OTG device, for storage, playing back and other applications.

Abstract translation: 网络摄像机包括拍摄外部图像的图像传感器; 传感器接口，其连接到法师传感器，以将图像传感器拍摄的图像接收并转换为数字图像数据; 至少一个压缩模块，其连接到传感器接口以将数字图像数据接收并压缩成压缩图像数据; 以及USB接口，其连接到压缩模块以将压缩的图像数据输出到具有诸如计算机和USB OTG设备的USB接口端口的主机设备，用于存储，回放和其他应用。

公开(公告)号：US07592619B2

公开(公告)日：2009-09-22

申请号：US11622490

申请日：2007-01-12

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: H01L29/15

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US20090000908A1

公开(公告)日：2009-01-01

申请号：US12218625

申请日：2008-07-15

Applicant: Michael D. Brain ,  Chun-Chieh Lin

Inventor： Michael D. Brain ,  Chun-Chieh Lin

IPC: B65G49/07 ,  G06F7/00

CPC classification number: B65G37/005 ,  B65G37/02 ,  B65G2201/0297 ,  H01L21/67276 ,  H01L21/67715 ,  H01L21/67769

Abstract: A system for buffering articles in transport is provided. The system comprises a buffer module configured to buffer articles and a computing system. The buffer module includes a first conveyor configured to transport the articles and a transference node configured to transfer the articles between the first conveyor and an external location. The computing system is configured to maintain an inventory list including a present location of each of the articles buffered by the buffer module. The computing system is further configured to control operation of the buffer module to transfer a selected article among the buffered articles to the external location.

Abstract translation: 提供了一种用于在运输中缓冲物品的系统。 该系统包括被配置为缓冲物品和计算系统的缓冲模块。 缓冲器模块包括构造成输送物品的第一传送器和被配置成在第一传送器和外部位置之间传送物品的传送节点。 计算系统被配置为维护包括由缓冲器模块缓冲的每个文章的当前位置的清单列表。 计算系统还被配置为控制缓冲器模块的操作以将缓冲的物品中的所选物品传送到外部位置。