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141 条记录 (耗时 0.028 秒)

    Planarization of shallow trench isolation (STI)
    11.
    发明授权
    Planarization of shallow trench isolation (STI) 有权
    浅沟槽隔离（STI）的平面化

    公开(公告)号：US06645825B1

    公开(公告)日：2003-11-11

    申请号：US09614554

    申请日：2000-07-12

    申请人： Chin Kun Lan ,  Ting Chun Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang

    发明人： Chin Kun Lan ,  Ting Chun Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang

    IPC分类号： H01L2176

    CPC分类号： H01L21/76229

    摘要： An improved and new process for fabricating a planarized structure of shallow trench isolation (STI) embedded in a silicon substrate has been developed. The planarizing method comprises a two-step CMP process in which the first CMP step comprises chemical-mechanical polishing of silicon oxide using a first polishing slurry which is selective to silicon oxide. The time of the second CMP step is determined by selecting an overpolish thickness based on the percentage of substrate area occupied by the trench. High manufacturing yield and superior planarity for silicon oxide STI are achieved.

    摘要翻译： 已经开发了一种用于制造嵌入硅衬底中的浅沟槽隔离（STI）的平面化结构的改进和新工艺。 平面化方法包括两步CMP工艺，其中第一CMP步骤包括使用对氧化硅选择性的第一抛光浆料进行二氧化硅的化学机械抛光。 通过基于沟槽占据的衬底面积的百分比来选择过抛光厚度来确定第二CMP步骤的时间。 实现了高的制造成品率和优异的氧化硅STI平坦度。

    Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity
    12.
    发明授权
    Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity 有权
    用于形成具有增强的膜厚度均匀性的微电子层的等离子体增强化学气相沉积（PECVD）方法

    公开(公告)号：US06281146B1

    公开(公告)日：2001-08-28

    申请号：US09396517

    申请日：1999-09-15

    申请人： Ying-Lang Wang ,  Hui-Ling Wang ,  Jowei Dun ,  Szu-An Wu

    发明人： Ying-Lang Wang ,  Hui-Ling Wang ,  Jowei Dun ,  Szu-An Wu

    IPC分类号： H01L2131

    CPC分类号： H01L21/02164 ,  C23C16/402 ,  C23C16/5096 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612

    摘要： A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.

    摘要翻译： 一种形成微电子层的方法。 首先提供基板。 然后在采用使用源材料气体和载气的等离子体增强化学气相沉积（PECVD）方法的基板上形成微电子层，其中采用足够低的等离子体功率，足够低的源材料气体：载体 气体流量比和足够高的载气原子质量，使得微电子层形成为具有增强的膜厚均匀性。 该方法可用于形成具有增强的膜厚度均匀性的离子注入屏幕层，例如氧化硅离子注入屏幕层。

    Obtaining the better defect performance of the fuse CMP process by adding slurry polish on more soft pad after slurry polish
    13.
    发明授权
    Obtaining the better defect performance of the fuse CMP process by adding slurry polish on more soft pad after slurry polish 有权
    通过在浆液抛光后在更软的垫上添加浆料抛光，获得熔融CMP工艺的更好的缺陷性能

    公开(公告)号：US06248002B1

    公开(公告)日：2001-06-19

    申请号：US09421509

    申请日：1999-10-20

    申请人： Hui-Ling Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang ,  Yu-Ku Lin

    发明人： Hui-Ling Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang ,  Yu-Ku Lin

    IPC分类号： B24B100

    CPC分类号： B24B37/042

    摘要： A method to prevent the accumulation of particle impurities on the surface of a semiconductor substrate that contains wolfram plugs during the process of polishing the surface of the wafer. The polishing sequence consists of three distinct polishing steps whereby the first two steps use hard polishing pads while the third step uses a soft polishing pad with the application of slurry during the third polish.

    摘要翻译： 一种在抛光晶片表面的过程中防止颗粒杂质在含有钨骨塞的半导体衬底表面积聚的方法。 抛光顺序由三个不同的抛光步骤组成，其中前两个步骤使用硬抛光垫，而第三步在第三次抛光期间使用软抛光垫施加浆料。

    Sensing product and method of making
    16.
    发明授权
    Sensing product and method of making 有权
    感知产品和制作方法

    公开(公告)号：US09419155B2

    公开(公告)日：2016-08-16

    申请号：US13343922

    申请日：2012-01-05

    申请人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

    发明人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC分类号： H01L31/0232 ,  H01L31/101 ,  H01L31/18

    CPC分类号： H01L31/0232 ,  H01L31/02327 ,  H01L31/101 ,  H01L31/18

    摘要： This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 μm.

    摘要翻译： 该描述涉及使用具有多个外延层的基板形成的感测产品。 至少第一外延层具有与第二外延层的组成不同的组成。 感测产品可选地包括第二外延层中的至少一个辐射感测元件以及可选地在第二外延层上的互连结构。 通过去除衬底和除第二外延层之外的所有外延层形成传感产物。 第二外延层的光入射表面具有小于约0.15μm的总厚度变化。

    Method and Apparatus for Backside Illumination Sensor
    17.
    发明申请
    Method and Apparatus for Backside Illumination Sensor 有权
    背面照明传感器的方法和装置

    公开(公告)号：US20130228886A1

    公开(公告)日：2013-09-05

    申请号：US13409924

    申请日：2012-03-01

    申请人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L31/0232 ,  H01L31/18

    CPC分类号： H01L27/1464 ,  H01L27/14687

    摘要： Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter.

    摘要翻译： 公开了用于背面照明（BSI）图像传感器装置的方法和装置。 在包括感光二极管的基板上形成BSI传感器装置。 衬底可以在背面变薄，则可以在衬底的背面上形成B掺杂的Epi-Si（Ge）层。 另外的层可以形成在B掺杂的Epi-Si（Ge）层上，例如金属屏蔽层，电介质层，微透镜和滤色器。

    STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
    18.
    发明申请
    STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING 有权
    应力半导体器件及其制造方法

    公开(公告)号：US20120292639A1

    公开(公告)日：2012-11-22

    申请号：US13111732

    申请日：2011-05-19

    申请人： Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L29/06 ,  H01L29/24 ,  H01L21/762

    CPC分类号： H01L21/823807 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262

    摘要： A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.

    摘要翻译： 公开了一种制造半导体器件的半导体器件和方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供衬底并在衬底上形成电介质层。 该方法还包括在电介质层内形成第一沟槽，其中第一沟槽延伸穿过电介质层并且外延（epi）在第一沟槽内生长第一有源层，并用辐射能选择性地固化与第一沟槽相邻的介电层 活动层

    Via/contact and damascene structures and manufacturing methods thereof
    19.
    发明授权
    Via/contact and damascene structures and manufacturing methods thereof 有权
    通孔/接触和镶嵌结构及其制造方法

    公开(公告)号：US08247322B2

    公开(公告)日：2012-08-21

    申请号：US11680981

    申请日：2007-03-01

    申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76831 ,  H01L21/7684

    摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

    摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。