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110 条记录 (耗时 0.031 秒)

    Semiconductor memory having trench capacitor formed with sheath electrode
    11.
    发明授权
    Semiconductor memory having trench capacitor formed with sheath electrode 失效
    具有形成有护套电极的沟槽电容器的半导体存储器

    公开(公告)号：US4918502A

    公开(公告)日：1990-04-17

    申请号：US123235

    申请日：1987-11-20

    申请人： Toru Kaga ,  Shinichiro Kimura ,  Hideo Sunami

    发明人： Toru Kaga ,  Shinichiro Kimura ,  Hideo Sunami

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10829

    摘要： The present invention relates to a highly packaged semiconductor memory, and more particularly to a memory cell having a trench capacitor for use in a CMOS memory. The present invention discloses a semiconductor memory employing memory cells each constructed of a trench type charge storage capacitor formed within a substrate, and a switching transistor; one electrode of the capacitor having a sheath-shaped structure which is electrically continuous with the Si substrate at a bottom of a groove and whose sideward periphery is covered with an insulator, the other electrode of the capacitor having a part which is buried inside the sheath electrode and another part which is electrically connected with an impurity diffused layer to function as a source region of the transistor. Further, a structure in which a voltage of 1/2 V.sub.cc can be applied to a plate electrode of a memory cell having a trench capacitor is disclosed.

    摘要翻译： 本发明涉及高度封装的半导体存储器，更具体地说，涉及一种具有用于CMOS存储器的沟槽电容器的存储单元。 本发明公开了一种半导体存储器，其采用由形成在衬底内的沟槽型电荷存储电容器构成的存储单元和开关晶体管; 电容器的一个电极具有鞘状结构，其在沟槽的底部与Si衬底电连接，并且其侧面被绝缘体覆盖，电容器的另一个电极具有埋在护套内的部分 电极和与杂质扩散层电连接以用作晶体管的源极区的另一部分。 此外，公开了可以向具有沟槽电容器的存储单元的板电极施加1/2Vcc的电压的结构。

    Dynamic random access memory having buried word lines
    12.
    发明授权
    Dynamic random access memory having buried word lines 失效
    具有掩埋字线的动态随机存取存储器

    公开(公告)号：US4873560A

    公开(公告)日：1989-10-10

    申请号：US155698

    申请日：1988-02-16

    申请人： Hideo Sunami ,  Shinichiro Kimura ,  Toru Kaga

    发明人： Hideo Sunami ,  Shinichiro Kimura ,  Toru Kaga

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10841 ,  Y10S257/922

    摘要： This invention relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the sidewall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate.

    摘要翻译： 本发明涉及一种非常大规模的动态随机存取存储器，并且公开了一种在器件表面部分上具有减小的步长并且几乎不受入射放射线影响的存储单元。 在由在半导体衬底中钻出的深孔组成的半导体存储器中，形成在深孔下半部分的侧壁部分上的电容器和形成在电容器上方的开关晶体管，至少形成一条字线的一半构成 开关晶体管的栅极被埋在形成在半导体衬底的表面部分处的细长凹部中。

    Semiconductor memory having stacked capacitor
    13.
    发明授权
    Semiconductor memory having stacked capacitor 失效
    半导体存储器具有层叠电容

    公开(公告)号：US5012310A

    公开(公告)日：1991-04-30

    申请号：US566315

    申请日：1990-08-13

    申请人： Shinichiro Kimura ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Hideo Sunami

    发明人： Shinichiro Kimura ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Hideo Sunami

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10808

    摘要： A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.

    摘要翻译： 公开了一种实现高集成度和高​​可靠性的兆比特动态随机存取存储器。 消除了对制造堆叠式电容器存储单元进行的光掩模对准的允许的需要。 每个存储单元的平板电极通过绝缘膜与存储器阵列中的对应数据线隔离，该绝缘膜自行设置在平板电极周围。

    Method for formation of insulation film on silicon buried in trench
    14.
    发明授权
    Method for formation of insulation film on silicon buried in trench 失效
    在埋在沟槽中的硅上形成绝缘膜的方法

    公开(公告)号：US4873203A

    公开(公告)日：1989-10-10

    申请号：US221351

    申请日：1988-07-19

    申请人： Toru Kaga ,  Shinichiro Kimura ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Hideo Sunami

    发明人： Toru Kaga ,  Shinichiro Kimura ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Hideo Sunami

    IPC分类号： H01L27/04 ,  H01L21/316 ,  H01L21/32 ,  H01L21/334 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L29/66181 ,  H01L21/32 ,  H01L21/763

    摘要： An insulation film on silicon buried in a trench is prepared by forming a field oxide film by using a first Si.sub.3 N.sub.4 mask formed on a silicon substrate, forming a second Si.sub.3 N.sub.4 mask for formation of a trench, forming a trench in the silicon substrate by using the second Si.sub.3 N.sub.4 mask, burying polycrystalline silicon in the trench, removing the second Si.sub.3 N.sub.4 mask while leaving the first Si.sub.3 N.sub.4 mask and oxidizing the surface of the polycrystalline silicon buried in the trench by thermal oxidation. The so-formed insulation film on silicon buried in the trench has a uniform thickness and a high dielectric strength. The surface of the substrate at a part where an active element will be formed in the future is not oxidized.

    摘要翻译： 通过使用在硅衬底上形成的第一Si 3 N 4掩模形成场氧化膜，形成用于形成沟槽的第二Si 3 N 4掩模，通过使用硅衬底形成硅衬底中的沟槽来制备掩埋在沟槽中的硅上的绝缘膜 第二Si 3 N 4掩模，在沟槽中埋入多晶硅，除去第二Si 3 N 4掩模，同时留下第一Si 3 N 4掩模，并通过热氧化氧化掩埋在沟槽中的多晶硅的表面。 埋在沟槽中的硅上如此形成的绝缘膜具有均匀的厚度和高介电强度。 在将来将形成有源元件的部分处的基板的表面不被氧化。

    Semiconductor memory having writing and reading transistors, method of fabrication thereof, and method of use thereof
    17.
    发明授权
    Semiconductor memory having writing and reading transistors, method of fabrication thereof, and method of use thereof 失效
    具有写入和读取晶体管的半导体存储器，其制造方法及其使用方法

    公开(公告)号：US5357464A

    公开(公告)日：1994-10-18

    申请号：US22937

    申请日：1993-02-26

    申请人： Shuji Shukuri ,  Toru Koga ,  Shinichiro Kimura ,  Digh Hisamoto ,  Kazuhiko Sagara ,  Tokuo Kure ,  Eiji Takeda

    发明人： Shuji Shukuri ,  Toru Koga ,  Shinichiro Kimura ,  Digh Hisamoto ,  Kazuhiko Sagara ,  Tokuo Kure ,  Eiji Takeda

    IPC分类号： H01L27/10 ,  G11C11/401 ,  G11C11/402 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/40

    CPC分类号： G11C11/401 ,  H01L27/108

    摘要： Disclosed is a semiconductor memory having a self-amplifying cell structure, using (1) a writing transistor and (2) a reading transistor with a floating gate as a charge storage node for each memory cell, and a method of fabricating the memory cell. The writing transistor and reading transistor are of opposite conductivity type to each other; for example, the writing transistor uses a P-channel MOS transistor and the reading transistor (having the floating gate) uses an N-channel MOS transistor. The floating gate of the reading transistor is connected to a single bit line through a source-drain path of the writing transistor, the source-drain path of the reading transistor is connected between the single bit line and a predetermined potential, and the gate electrodes of the writing and reading transistors are connected to a single word line. At least the reading transistor can be formed in a trench, and the word line can be formed overlying the writing transistor and the reading transistor in the trench. Also disclosed is a method of operating the memory cell, wherein the voltage applied to the word line, in a standby condition, is intermediate to the voltage applied to the word line during the writing operation and during the reading operation.

    摘要翻译： 公开了具有自放大单元结构的半导体存储器，其使用（1）写入晶体管和（2）具有浮置栅极的读取晶体管作为每个存储单元的电荷存储节点，以及制造该存储单元的方法。 写入晶体管和读取晶体管彼此具有相反的导电类型; 例如，写入晶体管使用P沟道MOS晶体管，并且读取晶体管（具有浮置栅极）使用N沟道MOS晶体管。 读取晶体管的浮置栅极通过写入晶体管的源极 - 漏极连接到单个位线，读取晶体管的源极 - 漏极连接在单个位线和预定电位之间，并且栅电极 的写和读晶体管连接到单个字线。 至少读取晶体管可以形成在沟槽中，并且字线可以形成在沟槽中的写入晶体管和读取晶体管的上方。 还公开了一种操作存储单元的方法，其中在备用状态下施加到字线的电压在写入操作期间和在读取操作期间施加到字线的电压的中间。

    SEMICONDUCTOR NONVOLATILE MEMORY DEVICE
    18.
    发明申请
    SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
    半导体非易失性存储器件

    公开(公告)号：US20100232231A1

    公开(公告)日：2010-09-16

    申请号：US12787158

    申请日：2010-05-25

    申请人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    发明人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    IPC分类号： G11C16/06 ,  G11C11/34

    CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

    摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

    摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE
    19.
    发明申请
    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US20100135080A1

    公开(公告)日：2010-06-03

    申请号：US12648796

    申请日：2009-12-29

    申请人： Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    发明人： Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC分类号： G11C16/04 ,  H01L29/792

    CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。