公开(公告)号：US5012310A

公开(公告)日：1991-04-30

申请号：US566315

申请日：1990-08-13

申请人： Shinichiro Kimura ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Hideo Sunami

发明人： Shinichiro Kimura ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Hideo Sunami

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10808

摘要： A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.

摘要翻译： 公开了一种实现高集成度和高​​可靠性的兆比特动态随机存取存储器。 消除了对制造堆叠式电容器存储单元进行的光掩模对准的允许的需要。 每个存储单元的平板电极通过绝缘膜与存储器阵列中的对应数据线隔离，该绝缘膜自行设置在平板电极周围。

公开(公告)号：US4873203A

公开(公告)日：1989-10-10

申请号：US221351

申请日：1988-07-19

申请人： Toru Kaga ,  Shinichiro Kimura ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Hideo Sunami

发明人： Toru Kaga ,  Shinichiro Kimura ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Hideo Sunami

IPC分类号： H01L27/04 ,  H01L21/316 ,  H01L21/32 ,  H01L21/334 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L21/32 ,  H01L21/763

摘要： An insulation film on silicon buried in a trench is prepared by forming a field oxide film by using a first Si.sub.3 N.sub.4 mask formed on a silicon substrate, forming a second Si.sub.3 N.sub.4 mask for formation of a trench, forming a trench in the silicon substrate by using the second Si.sub.3 N.sub.4 mask, burying polycrystalline silicon in the trench, removing the second Si.sub.3 N.sub.4 mask while leaving the first Si.sub.3 N.sub.4 mask and oxidizing the surface of the polycrystalline silicon buried in the trench by thermal oxidation. The so-formed insulation film on silicon buried in the trench has a uniform thickness and a high dielectric strength. The surface of the substrate at a part where an active element will be formed in the future is not oxidized.

摘要翻译： 通过使用在硅衬底上形成的第一Si 3 N 4掩模形成场氧化膜，形成用于形成沟槽的第二Si 3 N 4掩模，通过使用硅衬底形成硅衬底中的沟槽来制备掩埋在沟槽中的硅上的绝缘膜 第二Si 3 N 4掩模，在沟槽中埋入多晶硅，除去第二Si 3 N 4掩模，同时留下第一Si 3 N 4掩模，并通过热氧化氧化掩埋在沟槽中的多晶硅的表面。 埋在沟槽中的硅上如此形成的绝缘膜具有均匀的厚度和高介电强度。 在将来将形成有源元件的部分处的基板的表面不被氧化。

公开(公告)号：US5106775A

公开(公告)日：1992-04-21

申请号：US564470

申请日：1990-07-30

申请人： Toru Kaga ,  Yoshifumi Kawamoto ,  Hideo Sunami

发明人： Toru Kaga ,  Yoshifumi Kawamoto ,  Hideo Sunami

IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/311 ,  H01L21/334 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/06 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28211 ,  H01L21/31111 ,  H01L27/10841 ,  H01L27/10864 ,  H01L29/0657 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/51

摘要： A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO.sub.2 island is oxidized adjacent its lower end to insulate the island from the substrate.

公开(公告)号：US4967247A

公开(公告)日：1990-10-30

申请号：US279350

申请日：1988-12-02

申请人： Toru Kaga ,  Yoshifumi Kawamoto ,  Hideo Sunami

发明人： Toru Kaga ,  Yoshifumi Kawamoto ,  Hideo Sunami

IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/311 ,  H01L21/334 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/06 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28211 ,  H01L21/31111 ,  H01L27/10841 ,  H01L27/10864 ,  H01L29/0657 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/51

摘要： A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO.sub.2 island is oxidized adjacent its lower end to insulate the island from the substrate.

摘要翻译： 半导体存储器包括分别设置在每个半导体岛的上侧和下侧的开关器件和电荷存储器件。 这些岛形成在通过绝缘体与半导体衬底完全隔离的半导体衬底上。 开关装置和充电存储装置的宽度基本相同。 存储单元结构非常小。 细胞结构对α粒子具有高度抗性，并形成自对准。 在制造期间，SiO 2岛在其下端附近被氧化，以使岛与衬底绝缘。

公开(公告)号：US4918502A

公开(公告)日：1990-04-17

申请号：US123235

申请日：1987-11-20

申请人： Toru Kaga ,  Shinichiro Kimura ,  Hideo Sunami

发明人： Toru Kaga ,  Shinichiro Kimura ,  Hideo Sunami

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： The present invention relates to a highly packaged semiconductor memory, and more particularly to a memory cell having a trench capacitor for use in a CMOS memory. The present invention discloses a semiconductor memory employing memory cells each constructed of a trench type charge storage capacitor formed within a substrate, and a switching transistor; one electrode of the capacitor having a sheath-shaped structure which is electrically continuous with the Si substrate at a bottom of a groove and whose sideward periphery is covered with an insulator, the other electrode of the capacitor having a part which is buried inside the sheath electrode and another part which is electrically connected with an impurity diffused layer to function as a source region of the transistor. Further, a structure in which a voltage of 1/2 V.sub.cc can be applied to a plate electrode of a memory cell having a trench capacitor is disclosed.

摘要翻译： 本发明涉及高度封装的半导体存储器，更具体地说，涉及一种具有用于CMOS存储器的沟槽电容器的存储单元。 本发明公开了一种半导体存储器，其采用由形成在衬底内的沟槽型电荷存储电容器构成的存储单元和开关晶体管; 电容器的一个电极具有鞘状结构，其在沟槽的底部与Si衬底电连接，并且其侧面被绝缘体覆盖，电容器的另一个电极具有埋在护套内的部分 电极和与杂质扩散层电连接以用作晶体管的源极区的另一部分。 此外，公开了可以向具有沟槽电容器的存储单元的板电极施加1/2Vcc的电压的结构。

公开(公告)号：US4873560A

公开(公告)日：1989-10-10

申请号：US155698

申请日：1988-02-16

申请人： Hideo Sunami ,  Shinichiro Kimura ,  Toru Kaga

发明人： Hideo Sunami ,  Shinichiro Kimura ,  Toru Kaga

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10841 ,  Y10S257/922

摘要： This invention relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the sidewall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate.

摘要翻译： 本发明涉及一种非常大规模的动态随机存取存储器，并且公开了一种在器件表面部分上具有减小的步长并且几乎不受入射放射线影响的存储单元。 在由在半导体衬底中钻出的深孔组成的半导体存储器中，形成在深孔下半部分的侧壁部分上的电容器和形成在电容器上方的开关晶体管，至少形成一条字线的一半构成 开关晶体管的栅极被埋在形成在半导体衬底的表面部分处的细长凹部中。

公开(公告)号：US5357131A

公开(公告)日：1994-10-18

申请号：US93033

申请日：1993-07-19

申请人： Hideo Sunami ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Masao Tamura ,  Masanobu Miyao

发明人： Hideo Sunami ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Masao Tamura ,  Masanobu Miyao

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/0337 ,  H01L21/3086 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10841

摘要： A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.

摘要翻译： 一种半导体存储器，其中每个电容器的一部分形成在由形成在半导体衬底中的凹部包围的岛状区域的侧壁上，并且岛状区域和其它区域通过凹部电隔离。

公开(公告)号：US06355517B1

公开(公告)日：2002-03-12

申请号：US08172101

申请日：1993-12-23

申请人： Hideo Sunami ,  Tokuo Kure ,  Yoshifumi Kawamoto

发明人： Hideo Sunami ,  Tokuo Kure ,  Yoshifumi Kawamoto

IPC分类号： H01L218242

CPC分类号： G11C11/404 ,  H01L27/10829

摘要： A semiconductor memory having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor and suppressing expansion of a depletion layer from the groove, and a method for fabricating the same are disclosed. An area occupied by each memory cell can be made very small and a distance between the memory cells can also be made very small, accordingly, high density integration is facilitated.

摘要翻译： 公开了一种半导体存储器，其具有通过利用形成在半导体衬底中的沟槽和绝缘栅场效应晶体管而形成的电容器，并且抑制了耗尽层从沟槽的膨胀及其制造方法。 可以使每个存储单元所占据的面积非常小，并且存储单元之间的距离也可以非常小，因此便于高密度集成。

公开(公告)号：US4984030A

公开(公告)日：1991-01-08

申请号：US201100

申请日：1988-05-31

申请人： Hideo Sunami ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Masao Tamura ,  Masanobu Miyao

发明人： Hideo Sunami ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Masao Tamura ,  Masanobu Miyao

IPC分类号： G11C11/401 ,  H01L21/033 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L21/763 ,  H01L21/033 ,  H01L27/10841

摘要： A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.

公开(公告)号：US5237528A

公开(公告)日：1993-08-17

申请号：US822325

申请日：1992-01-17

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： G11C11/404 ,  H01L27/10829 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

摘要翻译： 半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。 该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接 到绝缘栅场效应晶体管的源极或漏极。 提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层 底物。