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    Continuous plane of thin-film materials for a two-terminal cross-point memory
    13.
    发明授权
    Continuous plane of thin-film materials for a two-terminal cross-point memory 失效
    用于两端交叉点存储器的薄膜材料的连续平面

    公开(公告)号：US07742323B2

    公开(公告)日：2010-06-22

    申请号：US11881474

    申请日：2007-07-26

    Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

    Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

    IPC: G11C11/00

    CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165 ,  Y10S257/903

    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

    Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

    Device fabrication
    14.
    发明授权
    Device fabrication 有权
    器件制造

    公开(公告)号：US08569160B2

    公开(公告)日：2013-10-29

    申请号：US13665603

    申请日：2012-10-31

    Applicant: Darrell Rinerson ,  Robin Cheung

    Inventor： Darrell Rinerson ,  Robin Cheung

    IPC: H01L21/768

    CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

    Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

    DEVICE FABRICATION
    15.
    发明申请
    DEVICE FABRICATION 有权
    设备制造

    公开(公告)号：US20130059436A1

    公开(公告)日：2013-03-07

    申请号：US13665603

    申请日：2012-10-31

    Applicant: Darrell Rinerson ,  Robin Cheung

    Inventor： Darrell Rinerson ,  Robin Cheung

    IPC: H01L21/768

    CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

    Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

    Memory cell formation using ion implant isolated conductive metal oxide
    16.
    发明授权
    Memory cell formation using ion implant isolated conductive metal oxide 失效
    使用离子注入隔离导电金属氧化物的存储单元形成

    公开(公告)号：US08003511B2

    公开(公告)日：2011-08-23

    申请号：US12653851

    申请日：2009-12-18

    Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

    Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

    IPC: H01L21/44

    CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

    Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

    Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

    Device fabrication
    17.
    发明申请
    Device fabrication 失效
    器件制造

    公开(公告)号：US20100159688A1

    公开(公告)日：2010-06-24

    申请号：US12454322

    申请日：2009-05-15

    Applicant: Darrell Rinerson ,  Robin Cheung

    Inventor： Darrell Rinerson ,  Robin Cheung

    IPC: H01L21/768

    CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

    Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

    METHOD AND APPARATUS FOR PROVIDING INTRA-TOOL MONITORING AND CONTROL
    18.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING INTRA-TOOL MONITORING AND CONTROL 审中-公开
    提供工具监控和控制的方法和装置

    公开(公告)号：US20060235563A1

    公开(公告)日：2006-10-19

    申请号：US11420916

    申请日：2006-05-30

    Applicant: Suketu Parikh ,  Robin Cheung

    Inventor： Suketu Parikh ,  Robin Cheung

    IPC: G06F19/00

    CPC classification number: H01L22/20 ,  G05B19/4187 ,  G05B19/41875 ,  G05B2219/32179 ,  G05B2219/32182 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/205 ,  Y02P90/22

    Abstract: An apparatus for performing intra-tool monitoring and control within a multi-step processing system. The apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer. As such, the output of the metrology data analyzer provides control parameters to process controllers connected controllers connected to each of the tools within the semiconductor wafer processing system. Consequently, the operation of the metrology stations and the metrology data analyzer provides both feed forward and feed back data to control the tools based upon certain information that is gathered within the metrology station.

    Abstract translation: 一种用于在多步骤处理系统内执行工具内监视和控制的装置。 该设备提供位于多个半导体晶片处理工具中的每一个之间的计量站，使得可以在晶片从一个工具传递到提供内部工具监视的另一个工具时进行测量。 由计量站收集的数据耦合到度量数据分析器，该测量数据分析器确定是否应该调整多个晶片处理工具中的任何一个以改善整个晶片的处理。 因此，测量数据分析仪的输出提供控制参数以处理连接到半导体晶片处理系统内的每个工具的控制器连接的控制器。 因此，计量站和度量数据分析仪的操作提供前馈和反馈数据，以基于在计量站内收集的某些信息来控制工具。

    Method for achieving copper fill of high aspect ratio interconnect features
    20.
    发明授权
    Method for achieving copper fill of high aspect ratio interconnect features 有权
    实现高宽比互连特征铜填充的方法

    公开(公告)号：US06436267B1

    公开(公告)日：2002-08-20

    申请号：US09650108

    申请日：2000-08-29

    Applicant: Daniel A. Carl ,  Barry Chin ,  Liang Chen ,  Robin Cheung ,  Peijun Ding ,  Yezdi Dordi ,  Imran Hashim ,  Peter Hey ,  Ashok K. Sinha

    Inventor： Daniel A. Carl ,  Barry Chin ,  Liang Chen ,  Robin Cheung ,  Peijun Ding ,  Yezdi Dordi ,  Imran Hashim ,  Peter Hey ,  Ashok K. Sinha

    IPC: C23C2802

    CPC classification number: H01L21/2885 ,  H01L21/76877

    Abstract: One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.

    Abstract translation: 本发明的一个方面提供一致的金属电镀技术，以在半导体衬底上形成亚微米高纵横比特征的无空隙金属互连。 本发明的一个实施方案提供了一种用于在基底上填充亚微米特征的方法，包括反应性预清洗基底，使用高密度等离子体物理气相沉积在基底上沉积阻挡层; 使用高密度等离子体物理气相沉积在阻挡层上沉积种子层; 以及使用高电阻电解质电化学沉积金属，并且在第一周期期间在第一沉积期间施加第一电流密度，然后施加第二电流密度。

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