公开(公告)号：US06977208B2

公开(公告)日：2005-12-20

申请号：US10766460

申请日：2004-01-27

Applicant: Davide Chiola

Inventor： Davide Chiola

IPC: H01L21/329 ,  H01L21/763 ,  H01L27/08 ,  H01L27/095 ,  H01L29/06 ,  H01L29/872 ,  H01L21/28

CPC classification number: H01L29/8725 ,  H01L21/763 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0692 ,  H01L29/66143 ,  H01L29/872

Abstract: A trench schottky diode which includes a thin insulation layer on the sidewalls of its trenches and a relatively thicker insulation layer at the bottoms of its trenches.

Abstract translation: 沟槽肖特基二极管，其在其沟槽的侧壁上包括薄的绝缘层，在其沟槽的底部包括相对较厚的绝缘层。

公开(公告)号：US20050161759A1

公开(公告)日：2005-07-28

申请号：US10766466

申请日：2004-01-27

Applicant: Davide Chiola ,  Kohji Andoh ,  Silvestro Fimiani

Inventor： Davide Chiola ,  Kohji Andoh ,  Silvestro Fimiani

IPC: H01L27/08 ,  H01L29/868 ,  H01L27/095

CPC classification number: H01L29/872 ,  H01L27/0814 ,  H01L29/0684 ,  H01L29/868

Abstract: A Merged P-i-N Schottky device in which the oppositely doped diffusions extend to a depth and have been spaced apart such that the device is capable of absorbing a reverse avalanche energy comparable to a Fast Recovery Epitaxial Diode having a comparatively deeper oppositely doped diffusion region.

Abstract translation: 合并的P-i-N肖特基器件，其中相反掺杂的扩散延伸到深度并且已经间隔开，使得该器件能够吸收与具有相对更深的相反掺杂扩散区域的快速恢复外延二极管相当的反向雪崩能量。

公开(公告)号：US06855593B2

公开(公告)日：2005-02-15

申请号：US10193783

申请日：2002-07-11

Applicant: Kohji Andoh ,  Davide Chiola

Inventor： Kohji Andoh ,  Davide Chiola

IPC: H01L21/329 ,  H01L27/08 ,  H01L29/40 ,  H01L29/47 ,  H01L29/872 ,  H01L21/8234

CPC classification number: H01L29/407 ,  H01L27/0814 ,  H01L29/66143 ,  H01L29/8725 ,  Y10S438/963

Abstract: A fabrication process for a Schottky barrier structure includes forming a nitride layer directly on a surface of an epitaxial (“epi”) layer and subsequently forming a plurality of trenches in the epi layer. The interior walls of the trenches are then deposited with a final oxide layer without forming a sacrificial oxide layer to avoid formation of a beak bird at the tops of the interior trench walls. A termination trench is etched in the same process step for forming the plurality of trenches in the active area.

Abstract translation: 用于肖特基势垒结构的制造方法包括在外延（“epi”）层的表面上直接形成氮化物层，随后在外延层中形成多个沟槽。 然后将沟槽的内壁沉积有最终的氧化物层，而不形成牺牲氧化物层，以避免在内部沟槽壁的顶部形成喙鸟。 在用于在有源区域中形成多个沟槽的相同工艺步骤中蚀刻端接沟槽。

公开(公告)号：US20130334677A1

公开(公告)日：2013-12-19

申请号：US13517654

申请日：2012-06-14

Applicant: Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

Inventor： Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/34

CPC classification number: H01L23/49562 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4952 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/11 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/4903 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H05K1/0296 ,  H05K3/308 ,  H05K2201/0792 ,  H05K2201/10166 ,  H05K2201/10522 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.

Abstract translation: 根据本发明的实施例，半导体模块包括具有包括第一栅极/基极引线，第一漏极/集电极引线和第一源极/发射极引线的第一多个引线的第一半导体器件。 该模块还包括第二半导体器件和电路板。 第二半导体器件具有包括第二栅极/基极引线，第二漏极/集电极引线和第二源极/发射极引线的第二多个引线。 电路板具有多个安装孔，其中第一多个引线和第二多个引线中的每一个安装到多个安装孔中的相应一个安装孔中。 在多个安装孔处，从第一栅极/基极引线到第二栅极/基极引线的第一距离与从第一源极/发射极引线到第二源极/发射极引线的第二距离不同。

公开(公告)号：US07655977B2

公开(公告)日：2010-02-02

申请号：US11252642

申请日：2005-10-18

Applicant: Chiu Ng ,  Davide Chiola

Inventor： Chiu Ng ,  Davide Chiola

IPC: H01L23/62

CPC classification number: H01L29/7397 ,  H01L29/402 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An IGBT for controlling the application of power to a plasma display panel has an increased current conduction capability and a reduced conduction loss at the expense of a reduced safe operating area. For a device with a 300 volt breakdown voltage rating, the die has a substrate resistivity less than 10 m ohm cm; a buffer layer thickness of about 8 μm resistivity in the range of 0.05 to 0.10 ohm cm, and an epi layer for receiving junction patterns and trenches, which has a thickness of from 31 to 37 μm and resistivity in te range of 14 to 18 ohm cm.

Abstract translation: 用于控制对等离子体显示面板的电力施加的IGBT具有增加的导电能力和降低的传导损耗，而降低安全操作区域。 对于具有300伏击穿电压额定值的器件，裸片具有小于10mΩcm的衬底电阻; 具有约0.05μm至0.10欧姆cm范围内的约8μm电阻率的缓冲层厚度，以及用于接收结形图案和沟槽的外延层，其厚度为31至37μm，电阻率范围为14至18欧姆 厘米。

公开(公告)号：US07510953B2

公开(公告)日：2009-03-31

申请号：US11255745

申请日：2005-10-21

Applicant: Donald He ,  Ritu Sodhi ,  Davide Chiola

Inventor： Donald He ,  Ritu Sodhi ,  Davide Chiola

IPC: H01L21/28

CPC classification number: H01L29/7813 ,  H01L27/0629 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8725

Abstract: A semiconductor device including a schottky device and a trench type semiconductor switching device such as a MOSFET formed in a common die.

Abstract translation: 一种半导体器件，包括肖特基器件和沟槽型半导体开关器件，例如形成在公共管芯中的MOSFET。

公开(公告)号：US07196397B2

公开(公告)日：2007-03-27

申请号：US11073123

申请日：2005-03-04

Applicant: Davide Chiola ,  He Zhi ,  Kohji Andoh ,  Daniel M. Kinzer

Inventor： Davide Chiola ,  He Zhi ,  Kohji Andoh ,  Daniel M. Kinzer

IPC: H01L27/02 ,  H01L27/04 ,  H01L21/02

CPC classification number: H01L29/7811 ,  H01L27/08 ,  H01L27/0802 ,  H01L29/405 ,  H01L29/407 ,  H01L29/7813 ,  H01L29/872

Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Abstract translation: 一种具有终端结构的半导体器件，其包括设置在螺旋沟槽内并连接在该器件的两个电源极之间的至少一个螺旋电阻器。

公开(公告)号：US06987305B2

公开(公告)日：2006-01-17

申请号：US10633824

申请日：2003-08-04

Applicant: Donald He ,  Ritu Sodhi ,  Davide Chiola

Inventor： Donald He ,  Ritu Sodhi ,  Davide Chiola

IPC: H01L29/76

CPC classification number: H01L29/7813 ,  H01L27/0629 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8725

Abstract: A semiconductor device including a schottky device and a trench type semiconductor switching device such as a MOSFET formed in a common die.

Abstract translation: 一种半导体器件，包括肖特基器件和沟槽型半导体开关器件，例如形成在公共管芯中的MOSFET。

公开(公告)号：US20050029585A1

公开(公告)日：2005-02-10

申请号：US10633824

申请日：2003-08-04

Applicant: Donald He ,  Ritu Sodhi ,  Davide Chiola

Inventor： Donald He ,  Ritu Sodhi ,  Davide Chiola

IPC: H01L29/872 ,  H01L21/329 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8248 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L27/0629 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8725

Abstract: A semiconductor device including a schottky device and a trench type semiconductor switching device such as a MOSFET formed in a common die.

Abstract translation: 一种半导体器件，包括肖特基器件和沟槽型半导体开关器件，例如形成在公共管芯中的MOSFET。

公开(公告)号：US06846729B2

公开(公告)日：2005-01-25

申请号：US10254112

申请日：2002-09-25

Applicant: Kohji Andoh ,  Davide Chiola ,  Daniel M. Kinzer

Inventor： Kohji Andoh ,  Davide Chiola ,  Daniel M. Kinzer

IPC: H01L27/08 ,  H01L21/425

CPC classification number: H01L27/0814 ,  H01L29/66143 ,  H01L29/8725

Abstract: A Schottky diode is adjusted by implanting an implant species by way of a titanium silicide Schottky contact and driving the implant species into the underlying silicon substrate by a rapid anneal. The implant is at a low energy, (e.g. about 10 keV) and at a low dose (e.g. less than about 9E12 atoms per cm2) such that the barrier height is slightly increased and the leakage current reduced without forming pn junction and retaining the peak boron concentration in the titanium silicide layer.

Abstract translation: 通过用硅化钛肖特基接触注入植入物种并通过快速退火将植入物种驱动到下面的硅衬底中来调节肖特基二极管。 植入物处于低能量（例如约10keV）和低剂量（例如小于约9E12原子/ cm 2），使得势垒高度略微增加，并且漏电流减小而不形成pn结，并且 保留钛硅化物层中的峰值硼浓度。