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26 条记录 (耗时 0.022 秒)

    Methods for single pass parallel hierarchical timing closure of integrated circuit designs
    11.
    发明授权
    Methods for single pass parallel hierarchical timing closure of integrated circuit designs 有权
    集成电路设计的单程并行分层定时闭合方法

    公开(公告)号：US08935642B1

    公开(公告)日：2015-01-13

    申请号：US13716127

    申请日：2012-12-15

    申请人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

    发明人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

    摘要： In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

    摘要翻译： 在本发明的一个实施例中，一种方法包括将集成电路设计划分成顶层和多个分区的层级，其中顶层包括顶级网表，每个分区包括分区网表; 接收所述集成电路设计的所述多个分区中的每一个的数据路径定时预算和时钟路径时序预算; 以及响应于相应的数据路径定时预算和时钟路径定时预算，生成每个分区的定时预算模型，其中每个定时预算模型包括用于每个相应分区的分区内时钟定时约束，用于独立实现顶层。

    Screening method for double pass screening
    14.
    发明授权
    Screening method for double pass screening 失效
    双程筛选筛选方法

    公开(公告)号：US06631675B2

    公开(公告)日：2003-10-14

    申请号：US09845070

    申请日：2001-04-27

    申请人： Jeffrey A. Brody ,  Harry D. Cox ,  John J. Garant ,  Dinesh Gupta ,  Dale W. Snowdon

    发明人： Jeffrey A. Brody ,  Harry D. Cox ,  John J. Garant ,  Dinesh Gupta ,  Dale W. Snowdon

    IPC分类号： B41M112

    CPC分类号： B41M1/12 ,  B41M3/006 ,  B41N1/24 ,  H05K1/0306 ,  H05K3/1225 ,  H05K3/4061 ,  H05K2203/1476

    摘要： A screening mask for screening an article, the screening mask including a screening mask body having a screening side and a nonscreening side, an one opening through the mask for screening at least one feature from the screening side to the nonscreening side, and a blind opening for protecting a previously screened feature. The blind opening is blocked on the screening side and open on the nonscreening side. The screening mask is used in double pass screening so that a second feature may be formed on the article without damaging a previously formed feature.

    摘要翻译： 一种用于筛选物品的筛选掩模，所述筛选掩模包括具有筛选侧和非筛选侧的筛选面罩主体，通过掩模的一个开口用于筛选从筛选侧至非筛选侧的至少一个特征，以及盲孔 用于保护先前筛选的功能。 盲孔在屏蔽侧被阻挡，并在非屏蔽侧打开。 筛选掩模用于双程筛选，使得可以在制品上形成第二特征而不损害先前形成的特征。

    Method for making ceramic substrates from thin and thick ceramic greensheets
    15.
    发明授权
    Method for making ceramic substrates from thin and thick ceramic greensheets 失效
    从薄而厚的陶瓷板制造陶瓷基板的方法

    公开(公告)号：US5601672A

    公开(公告)日：1997-02-11

    申请号：US333010

    申请日：1994-11-01

    申请人： Jon A. Casey ,  Dinesh Gupta ,  James R. Wylder

    发明人： Jon A. Casey ,  Dinesh Gupta ,  James R. Wylder

    IPC分类号： C04B35/111 ,  C04B35/622 ,  H01L21/48 ,  H01L23/538 ,  H05K1/03 ,  H05K3/40 ,  H05K3/46 ,  B32B31/12 ,  B32B31/26

    CPC分类号： H05K3/4629 ,  C04B35/111 ,  C04B35/62218 ,  H01L21/4857 ,  H01L23/5383 ,  H05K3/462 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2203/063 ,  H05K3/4061 ,  H05K3/4623 ,  Y10T156/1056 ,  Y10T29/49163

    摘要： Method for producing ceramic laminates from a plurality of greensheet layers which include one or more thin greensheet layers, e.g. having a thickness less than about 3 mils, with interposed patterned circuit layers and conductive vias, while avoiding the loss of strength and the distortion encountered when paste compositions are pre-applied to such thin greensheet layers. The invention avoids the aforementioned problems by the use of a plurality of greensheet layers including thicker, paste-resistant greensheet layers having a thickness greater than the thin greensheet layer, e.g., between 5 and 10 mils, each pair of the thicker greensheet layers confining therebetween an unscreened thin greensheet layer, one of the thicker greensheet layers also being screened with the circuit pattern layer normally applied to the interposed thin greensheet layer. Thereafter the superposed layers are laminated and sintered to form the composite.

    摘要翻译： 用于从多个毛坯层制造陶瓷层压板的方法，所述多个毛坯层包括一个或多个薄的毛坯层，例如， 具有小于约3密耳的厚度，具有插入的图案化电路层和导电通孔，同时避免了当将糊剂组合物预先施加到这种薄的毛坯层时遇到的强度损失和失真。 本发明通过使用多个毛坯层来避免上述问题，所述多个毛坯层包括厚度大于薄的毛坯层的厚度较大的耐膏状毛坯层，例如在5至10密耳之间，每对较厚的毛坯层限制在它们之间 未筛选的薄毛坯层，较厚的毛坯层之一也被通常施加到插入的薄毛坯层上的电路图案层进行筛选。 然后将叠层层压并烧结以形成复合材料。

    Catheter with Gills
    16.
    发明申请
    Catheter with Gills 审中-公开
    导管与鳃

    公开(公告)号：US20150265805A1

    公开(公告)日：2015-09-24

    申请号：US14628239

    申请日：2015-02-21

    申请人： Ahmad D. Vakili ,  Dinesh Gupta

    发明人： Ahmad D. Vakili ,  Dinesh Gupta

    IPC分类号： A61M25/00 ,  A61M5/00

    CPC分类号： A61M25/0075 ,  A61M25/0071 ,  A61M31/005 ,  A61M2025/0079

    摘要： A guide catheter has an inlet orifice that allows blood to enter an interior passage of the catheter. A valve is positioned next to the inlet orifice that selectively opens and closes the inlet orifice. The catheter includes a dye passage that transports dye from a proximal end of the catheter to a dye outlet orifice. The dye passage may be formed in a unitary tubular member, a partitioned tubular member or in the clearances of a double-walled catheter. A valve may also be positioned next to the dye outlet orifices that selectively opens and closes the orifices. The valves are preferably kidney-shaped expandable bladders or pressure valves. A capillary tube connected to the expandable bladder functions to inflate and deflate the expandable bladder. The expandable bladders and capillary tubes are incorporated into the wall of the catheter.

    摘要翻译： 引导导管具有允许血液进入导管的内部通道的入口孔口。 阀门定位在入口孔旁边，选择性地打开和关闭入口孔口。 导管包括将染料从导管的近端输送到染料出口孔的染料通道。 染色通道可以形成为整体管状构件，分隔的管状构件或双壁导管的间隙。 也可以将阀定位在选择性地打开和关闭孔口的染料出口孔旁边。 阀优选为肾形可膨胀气囊或压力阀。 连接到可膨胀气囊的毛细管用于使可膨胀气囊膨胀和放气。 可扩张的囊和毛细管并入导管的壁中。

    Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs
    17.
    发明授权
    Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs 有权
    集成电路设计的单程并行分层定时闭合的流程方法

    公开(公告)号：US08365113B1

    公开(公告)日：2013-01-29

    申请号：US12708530

    申请日：2010-02-18

    申请人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

    发明人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

    摘要： In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

    摘要翻译： 在本发明的一个实施例中，一种方法包括将集成电路设计划分成顶层和多个分区的层级，其中顶层包括顶级网表，每个分区包括分区网表; 接收所述集成电路设计的所述多个分区中的每一个的数据路径定时预算和时钟路径时序预算; 以及响应于相应的数据路径定时预算和时钟路径定时预算，生成每个分区的定时预算模型，其中每个定时预算模型包括用于每个相应分区的分区内时钟定时约束，用于独立实现顶层。

    Apparatus and method for repairing electronic packages
    19.
    发明授权
    Apparatus and method for repairing electronic packages 失效
    用于修理电子封装的装置和方法

    公开(公告)号：US06713686B2

    公开(公告)日：2004-03-30

    申请号：US10053362

    申请日：2002-01-18

    申请人： Wiren D. Becker ,  Dinesh Gupta ,  Sudipta K. Ray ,  Robert A. Rita ,  Herbert I. Stoller ,  Kathleen M. Wiley

    发明人： Wiren D. Becker ,  Dinesh Gupta ,  Sudipta K. Ray ,  Robert A. Rita ,  Herbert I. Stoller ,  Kathleen M. Wiley

    IPC分类号： H01R1204

    CPC分类号： H01L23/5382 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0292 ,  H05K1/113 ,  Y10T29/49155 ,  H01L2924/00

    摘要： A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.

    摘要翻译： 多芯片模块基板，其布置有在模块的芯片位置的修复通道之间延伸的修理通孔和修复线，通过该维修线可以进行修理以克服模块电路中的缺陷，以及用于实现该电路中的缺陷的修复的方法 模块。 在第一信号通孔，第二信号通孔以及在第一信号通孔和第二信号通孔之间延伸并且用于电连接第一信号通孔的电路线中的任何一个中可能会发生缺陷。 识别出故障电路后，电路的信号通孔被隔离。 然后，故障电路的第一信号通路经由具有第一信号的芯片位置的修复通孔经由与具有第二信号通路的芯片位置的修复通路连接，并且具有缺陷电路的第二信号通孔 电路经由具有第二信号的芯片位置的修复通路经由与经由具有第一信号通孔的芯片位置的修复通路相连接。

    Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints
    20.
    发明授权
    Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints 有权
    电路设计系统和从芯片级定时约束产生分级块级定时约束的方法

    公开(公告)号：US08977994B1

    公开(公告)日：2015-03-10

    申请号：US12983247

    申请日：2010-12-31

    申请人： Oleg Levitsky ,  Chien-Chu Kuo ,  Dinesh Gupta

    发明人： Oleg Levitsky ,  Chien-Chu Kuo ,  Dinesh Gupta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

    摘要： A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

    摘要翻译： 一种设计集成电路的系统和方法，该集成电路能够导出从芯片级定时约束和分析导出的集成电路的各个块级电路的时序约束。 块级定时约束是块级电路的输入和输出端口处的一个或多个逻辑时序约束点的形式。 每个逻辑时序约束点指定用于通过端口对数据进行时钟源的时钟源，从输入端口向后指定数据传播延迟并从输出端口转发的延迟参数以及与数据路径相关联的任何定时异常。 使用逻辑时序约束点，电路设计系统对每个块级电路进行独立的时序分析和优化。 然后，系统将块级电路重新组装成可以实现时序闭合的修改的芯片级电路。